"A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced ..."

Jawar Singh et al. (2010)

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DOI: 10.1109/ISQED.2010.5450397

access: closed

type: Conference or Workshop Paper

metadata version: 2020-03-27

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Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan:
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead. ISQED 2010: 131-138

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