"Performance modeling and optimization for on-chip interconnects in 3D ..."

Javaneh Mohseni, Chenyun Pan, Azad Naeemi (2016)

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DOI: 10.1109/ISQED.2016.7479209

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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Javaneh Mohseni, Chenyun Pan, Azad Naeemi:
Performance modeling and optimization for on-chip interconnects in 3D memory arrays. ISQED 2016: 252-257

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