"Testable Clock Routing Architecture for Field Programmable Gate Arrays."

L. Kalyan Kumar et al. (2003)

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DOI: 10.1007/978-3-540-45234-8_116

access: closed

type: Conference or Workshop Paper

metadata version: 2020-09-10

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L. Kalyan Kumar, Amol J. Mupid, Aditya S. Ramani, V. Kamakoti:
Testable Clock Routing Architecture for Field Programmable Gate Arrays. FPL 2003: 1044-1047

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