default search action
"A 22nm 56TOPS/W 6/8-bit Linearly-scalable R-2R Multiply-and-Accumulate ..."
Tianwen Tang, Antonio Liscidini (2023)
- Tianwen Tang, Antonio Liscidini:
A 22nm 56TOPS/W 6/8-bit Linearly-scalable R-2R Multiply-and-Accumulate Architecture with 2.2ns Latency. ESSCIRC 2023: 473-476
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.