default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDPaul Chow
Person information
- affiliation: University of Toronto, Canada
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j31]Paul Chow:
The Software-Centric Approach of SYNERGY: Technical Perspective. Commun. ACM 67(8): 133 (2024)- [i7]Mohammad Ewais, Paul Chow:
DDC: A Vision for a Disaggregated Datacenter. CoRR abs/2402.12742 (2024) - [i6]Yu Gao, Juan Camilo Vega, Paul Chow:
The Feasibility of Implementing Large-Scale Transformers on Multi-FPGA Platforms. CoRR abs/2404.16158 (2024) - 2023
- [j30]Mohammad Ewais
, Paul Chow:
Disaggregated Memory in the Datacenter: A Survey. IEEE Access 11: 20688-20712 (2023) - [c124]Qiangfeng Shen, Paul Chow:
A Lightweight Routing Layer Using a Reliable Link-Layer Protocol. CloudCom 2023: 82-90 - [c123]Mohammadmahdi Mazraeli, Yu Gao, Paul Chow:
Partitioning Large-Scale, Multi-FPGA Applications for the Data Center. FPL 2023: 253-258 - [i5]Qianfeng Shen, Jun Zheng, Paul Chow:
RIFL: A Reliable Link Layer Network Protocol for Data Center Communication. CoRR abs/2309.08696 (2023) - [i4]Qianfeng Shen, Paul Chow:
A Lightweight Routing Layer Using a Reliable Link-Layer Protocol. CoRR abs/2311.00911 (2023) - 2022
- [j29]Qianfeng Shen, Jun Zheng, Paul Chow:
RIFL: a reliable link layer network protocol for data center communication. JOCN 14(3): 111-126 (2022) - [j28]Naif Tarafdar, Giuseppe Di Guglielmo, Philip C. Harris, Jeffrey D. Krupa, Vladimir Loncar, Dylan S. Rankin, Nhan Tran, Zhenbin Wu, Qianfeng Shen, Paul Chow:
AIgean: An Open Framework for Deploying Machine Learning on Heterogeneous Clusters. ACM Trans. Reconfigurable Technol. Syst. 15(3): 23:1-23:32 (2022) - [j27]Christophe Bobda, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, Miriam Leeser, Martin C. Herbordt, Hafsah Shahzad, H. Peter Hofstee, Burkhard Ringlein, Jakub Szefer, Ahmed Sanaullah, Russell Tessier:
The Future of FPGA Acceleration in Datacenters and the Cloud. ACM Trans. Reconfigurable Technol. Syst. 15(3): 34:1-34:42 (2022) - [c122]Qianfeng Clark Shen, Juan Camilo Vega, Paul Chow:
Parallel CRC On An FPGA At Terabit Speeds. FPT 2022: 1-6 - 2021
- [j26]Jun Li, Paul Chow, Yuanxi Peng, Tian Jiang:
FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 259-272 (2021) - [c121]Juan Camilo Vega, Mohammad Ewais, Alberto Leon-Garcia, Paul Chow:
FFIVE: An FPGA Framework for Interactive VNF Environments. FCCM 2021: 263 - [c120]Arzhang Rafii, Paul Chow, Welson Sun:
Pharos: a Performance Monitor for Multi-FPGA Systems. FCCM 2021: 271 - [c119]Marco Antonio Merlini, Isamu Poy, Paul Chow:
Interactive Debugging at IP Block Interfaces in FPGAs. FPGA 2021: 138-144 - [c118]Qianfeng Clark Shen, Jun Zheng, Paul Chow:
RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPGA Communication. FPGA 2021: 148 - [c117]Varun Sharma, Paul Chow:
Exploring PGAS Communication for Heterogeneous Clusters with FPGAs. FPGA 2021: 225 - [c116]Arzhang Rafii, Welson Sun, Paul Chow:
Pharos: a Multi-FPGA Performance Monitor. FPL 2021: 257-262 - [c115]Mohammad Ewais, Juan Camilo Vega, Alberto Leon-Garcia, Paul Chow:
A Framework Integrating FPGAs in VNF Networks. NoF 2021: 1-9 - [e4]Christian Plessl, Paul Chow, Marco Platzner:
HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Virtual Event, Germany, 21-23 June, 2021. ACM 2021, ISBN 978-1-4503-8549-7 [contents] - [i3]Varun Sharma, Paul Chow:
A PGAS Communication Library for Heterogeneous Clusters. CoRR abs/2104.12350 (2021) - 2020
- [c114]Juan Camilo Vega, Marco Antonio Merlini, Paul Chow:
FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark. FCCM 2020: 47-55 - [c113]Charles Lo, Paul Chow:
Hierarchical Modelling of Generators in Design-Space Exploration. FCCM 2020: 186-194 - [c112]Juan Camilo Vega, Qianfeng Clark Shen, Paul Chow:
SHIP: Storage for Hybrid Interconnected Processors. FCCM 2020: 211 - [c111]Naif Tarafdar, Giuseppe Di Guglielmo, Philip C. Harris, Jeffrey D. Krupa, Vladimir Loncar, Dylan S. Rankin, Nhan Tran, Zhenbin Wu, Qianfeng Shen, Paul Chow:
AIgean: An Open Framework for Machine Learning on Heterogeneous Clusters. FCCM 2020: 239
2010 – 2019
- 2019
- [j25]Ehsan Ghasemi, Paul Chow:
Accelerating Apache Spark with FPGAs. Concurr. Comput. Pract. Exp. 31(2) (2019) - [c110]Varun Sharma, Naif Tarafdar, Paul Chow:
Sonar: Writing Testbenches through Python. FCCM 2019: 311 - [c109]Daniel Rozhko, Paul Chow:
The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs. FPGA 2019: 232-241 - [c108]Nariman Eskandari, Naif Tarafdar, Daniel Ly-Ma, Paul Chow:
A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center. FPGA 2019: 262-271 - [c107]Juan Camilo Vega, Qianfeng Shen, Alberto Leon-Garcia, Paul Chow:
Introducing ReCPRI: A Field Re-configurable Protocol for Backhaul Communication in a Radio Access Network. IM 2019: 329-336 - 2018
- [j24]Naif Tarafdar, Nariman Eskandari, Thomas Lin, Paul Chow:
Designing for FPGAs in the Cloud. IEEE Des. Test 35(1): 23-29 (2018) - [j23]Naif Tarafdar, Nariman Eskandari, Varun Sharma, Charles Lo, Paul Chow:
Galapagos: A Full Stack Approach to FPGA Integration in the Cloud. IEEE Micro 38(6): 18-24 (2018) - [c106]Abdul-Amir Yassine, Yasmin Afsharnejad, Omar Ragheb, Vaughn Betz, Paul Chow:
A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media. FCCM 2018: 216 - [c105]Charles Lo, Paul Chow:
Multi-fidelity Optimization for High-Level Synthesis Directives. FPL 2018: 272-279 - [c104]Yasmin Afsharnejad, Abdul-Amir Yassine, Omar Ragheb, Paul Chow, Vaughn Betz:
HLS-based FPGA Acceleration of Light Propagation Simulation in Turbid Media. HEART 2018: 11:1-11:6 - 2017
- [c103]Thomas Lin, Naif Tarafdar, Byungchul Park, Paul Chow, Alberto Leon-Garcia:
Enabling network function virtualization over heterogeneous resources. APNOMS 2017: 58-63 - [c102]Paul Chow:
Building the Reconfigurable Cloud Ecosystem. ETCD@ASPLOS 2017: 10:1 - [c101]Daniel Rozhko, Geoffrey Elliott, Daniel Ly-Ma, Paul Chow, Hans-Arno Jacobsen:
Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules. FPGA 2017: 201-206 - [c100]Naif Tarafdar, Thomas Lin, Eric Fukuda, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow:
Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center. FPGA 2017: 237-246 - [c99]Naif Tarafdar, Thomas Lin, Nariman Eskandari, David Lion, Alberto Leon-Garcia, Paul Chow:
Heterogeneous virtualized network function framework for the data center. FPL 2017: 1-8 - [c98]Zhiqiang Liu, Yong Dou, Jingfei Jiang, Qiang Wang, Paul Chow:
An FPGA-based processor for training convolutional neural networks. FPT 2017: 207-210 - [c97]Roberto DiCecco, Lin Sun, Paul Chow:
FPGA-based training of convolutional neural networks with a reduced precision floating-point library. FPT 2017: 239-242 - [c96]Vincent Mirian, Paul Chow:
Enabling FPGAs as a True Device in the OpenCL Standard: Bridging the Gap for FPGAs. IWOCL 2017: 5:1-5:12 - [c95]Fernando Martin del Campo, Paul Chow:
Task replication and control for highly parallel in-memory stores. MEMSYS 2017: 312-326 - [c94]Andrew Boutros, Brett Grady, Mustafa Abbas, Paul Chow:
Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis. ReConFig 2017: 1-6 - 2016
- [j22]Jianfeng Zhang, Paul Chow, Hengzhu Liu:
CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition. ACM Trans. Reconfigurable Technol. Syst. 9(2): 9:1-9:22 (2016) - [c93]Ehsan Ghasemi, Paul Chow:
Accelerating Apache Spark Big Data Analysis with FPGAs. FCCM 2016: 94 - [c92]Ehsan Ghasemi, Paul Chow:
A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only). FPGA 2016: 274 - [c91]Charles Lo, Paul Chow:
Model-based optimization of High Level Synthesis directives. FPL 2016: 1-10 - [c90]Roberto DiCecco, Griffin Lacey, Jasmina Vasiljevic, Paul Chow, Graham W. Taylor, Shawki Areibi:
Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks. FPT 2016: 265-268 - [c89]Vincent Mirian, Paul Chow:
Extracting Designs of Secure IPs Using FPGA CAD Tools. ACM Great Lakes Symposium on VLSI 2016: 293-298 - [c88]Ehsan Ghasemi, Paul Chow:
Accelerating Apache Spark Big Data Analysis with FPGAs. UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld 2016: 737-744 - [i2]Roberto DiCecco, Griffin Lacey, Jasmina Vasiljevic, Paul Chow, Graham W. Taylor, Shawki Areibi:
Caffeinated FPGAs: FPGA Framework For Convolutional Neural Networks. CoRR abs/1609.09671 (2016) - 2015
- [j21]Jianfeng Zhang, Paul Chow, Hengzhu Liu:
An Enhanced Adaptive Recoding Rotation CORDIC. ACM Trans. Reconfigurable Technol. Syst. 9(1): 4:1-4:25 (2015) - [c87]Stuart Byma, Naif Tarafdar, Talia Xu, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow:
Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware. FPGA 2015: 94-97 - [c86]Jasmina Vasiljevic, Ralph Wittig, Paul Schumacher, Jeff Fifield, Fernando Martinez-Vallina, Henry Styles, Paul Chow:
OpenCL library of stream memory components targeting FPGAs. FPT 2015: 104-111 - [c85]Vincent Mirian, Paul Chow:
Exploring pipe implementations using an OpenCL framework for FPGAs. FPT 2015: 112-119 - [c84]Jianfeng Zhang, Paul Chow, Hengzhu Liu:
FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC. FPT 2015: 128-135 - [c83]Fernando Martin del Campo, Paul Chow:
Architecture Exploration for Data Intensive Applications. MEMSYS 2015: 135-145 - [c82]Vincent Mirian, Paul Chow:
Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs. ReConFig 2015: 1-8 - [c81]Vincent Mirian, Paul Chow:
UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAs. ReConFig 2015: 1-6 - 2014
- [j20]Yuanxi Peng, Manuel Saldaña, Christopher A. Madill, Xiaofeng Zou, Paul Chow:
Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications. ACM Trans. Reconfigurable Technol. Syst. 7(3): 17:1-17:23 (2014) - [j19]Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei:
Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1054-1059 (2014) - [c80]Stuart Byma, J. Gregory Steffan, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow:
FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack. FCCM 2014: 109-116 - [c79]Jasmina Vasiljevic, Paul Chow:
MPack: global memory optimization for stream applications in high-level synthesis. FPGA 2014: 233-236 - [c78]Vincent Mirian, Paul Chow:
Using an OpenCL framework to evaluate interconnect implementations on FPGAs. FPL 2014: 1-4 - [c77]Jasmina Vasiljevic, Paul Chow:
Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use. FPL 2014: 1-8 - [c76]Jianfeng Zhang, Paul Chow, Hengzhu Liu:
An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC. FPT 2014: 123-130 - [c75]Ruediger Willenberg, Paul Chow:
A Heterogeneous GASNet Implementation for FPGA-accelerated Computing. PGAS 2014: 2:1-2:9 - [c74]Stuart Byma, Hadi Bannazadeh, Alberto Leon-Garcia, J. Gregory Steffan, Paul Chow:
Virtualized Reconfigurable Hardware Resources in the SAVI Testbed. TRIDENTCOM 2014: 54-64 - [i1]Ruediger Willenberg, Paul Chow:
A Software Parallel Programming Approach to FPGA-Accelerated Computing. CoRR abs/1408.4959 (2014) - 2013
- [c73]Ruediger Willenberg, Paul Chow:
A remote memory access infrastructure for global address space programming models in FPGAs. FPGA 2013: 211-220 - [c72]Stuart Byma, J. Gregory Steffan, Paul Chow:
NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract. FPL 2013: 1 - [c71]Ruediger Willenberg, Paul Chow:
Simulation-based HW/SW co-debugging for field-programmable systems-on-chip. FPL 2013: 1-8 - [c70]Ruediger Willenberg, Paul Chow:
SimXMD: Simulation-based HW/SW co-debugging. FPL 2013: 1 - [c69]Paul Chow:
Why Put FPGAs in your CPU socket? FPT 2013: 3 - [c68]Zhongduo Lin, Paul Chow:
ZCluster: A Zynq-based Hadoop cluster. FPT 2013: 450-453 - 2012
- [j18]Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow:
Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms. Int. J. Reconfigurable Comput. 2012: 127302:1-127302:10 (2012) - [c67]Vincent Mirian, Paul Chow:
FCache: a system for cache coherent processing on FPGAs. FPGA 2012: 233-236 - [c66]S. Alexander Chin, Paul Chow:
OpenCL memory infrastructure for FPGAs (abstract only). FPGA 2012: 269-270 - [c65]Zhongduo Lin, Charles Lo, Paul Chow:
K-means implementation on FPGA for high-dimensional data using triangle inequality. FPL 2012: 437-442 - [c64]Vincent Mirian, Paul Chow:
Managing mutex variables in a cache-coherent shared-memory system for FPGAs. FPT 2012: 43-46 - [c63]Charles Lo, Paul Chow:
A high-performance architecture for training Viola-Jones object detectors. FPT 2012: 174-181 - [c62]Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei:
Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method. FPT 2012: 190-197 - [c61]Ruediger Willenberg, Paul Chow:
SimXMD: Integrated debugging of C code and hardware components. FPT 2012: 309-312 - [c60]Vincent Mirian, Paul Chow:
An implementation of a directory protocol for a cache coherent system on FPGAs. ReConFig 2012: 1-6 - 2011
- [j17]Alexander Kaganov, Asif Lakhany, Paul Chow:
FPGA Acceleration of MultiFactor CDO Pricing. ACM Trans. Reconfigurable Technol. Syst. 4(2): 20:1-20:17 (2011) - [j16]Lesley Shannon, Paul Chow:
Leveraging reconfigurability in the hardware/software codesign process. ACM Trans. Reconfigurable Technol. Syst. 4(3): 28:1-28:27 (2011) - [c59]Charles Lo, Paul Chow:
Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI. FPGA 2011: 189-198 - [c58]Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang:
Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method. FPL 2011: 110-115 - [c57]Yuanxi Peng, Manuel Saldaña, Paul Chow:
Hardware Support for Broadcast and Reduce in MPSoC. FPL 2011: 144-150 - [e3]Paul Chow, Michael J. Wirthlin:
IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2011, Salt Lake City, Utah, USA, 1-3 May 2011. IEEE Computer Society 2011, ISBN 978-0-7695-4301-7 [contents] - 2010
- [j15]Daniel Le Ly, Paul Chow:
High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines. IEEE Trans. Neural Networks 21(11): 1780-1792 (2010) - [j14]Manuel Saldaña, Arun Patel, Christopher A. Madill, Daniel Nunes, Danyao Wang, Paul Chow, Ralph Wittig, Henry Styles, Andrew Putnam:
MPI as a Programming Model for High-Performance Reconfigurable Computers. ACM Trans. Reconfigurable Technol. Syst. 3(4): 22:1-22:29 (2010) - [c56]Andrew W. H. House, Manuel Saldaña, Paul Chow:
Integrating High-Level Synthesis into MPI. FCCM 2010: 175-178 - [c55]Dharmendra P. Gupta, Paul Chow:
Acceleration of an analytical approach to collateralized debt obligation pricing. FPGA 2010: 103-106 - [c54]Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow:
Using Partial Reconfiguration in an Embedded Message-Passing System. ReConFig 2010: 418-423 - [c53]Hadi Bannazadeh, Alberto Leon-Garcia, Keith Redmond, Gordon Tam, Arbab Khan, Mingliang Ma, Saleh Dani, Paul Chow:
Virtualized Application Networking Infrastructure. TRIDENTCOM 2010: 363-382
2000 – 2009
- 2009
- [j13]Manuel Saldaña, Emanuel Ramalho, Paul Chow:
A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems. Int. J. Reconfigurable Comput. 2009: 376232:1-376232:9 (2009) - [c52]Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose:
FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. FCCM 2009: 157-164 - [c51]Daniel Le Ly, Paul Chow:
A high-performance FPGA architecture for restricted boltzmann machines. FPGA 2009: 73-82 - [c50]Daniel Le Ly, Paul Chow:
A multi-FPGA architecture for stochastic Restricted Boltzmann Machines. FPL 2009: 168-173 - [c49]Daniel Le Ly, Manuel Saldaña, Paul Chow:
The challenges of using an embedded MPI for hardware-based processing nodes. FPT 2009: 120-127 - [c48]Paul Chow, Manuel Saldaña, Arun Patel, Christopher A. Madill:
Programming the Nallatech Xeon + multi-FPGA heterogeneous platform. Hot Chips Symposium 2009: 1-16 - [c47]Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing:
Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. ReConFig 2009: 48-53 - [e2]Paul Chow, Peter Y. K. Cheung:
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009. ACM 2009, ISBN 978-1-60558-410-2 [contents] - 2008
- [j12]Tor M. Aamodt, Paul Chow:
Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy. ACM Trans. Embed. Comput. Syst. 7(3): 26:1-26:27 (2008) - [c46]Andrew W. H. House, Paul Chow:
Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems. FCCM 2008: 291-292 - [c45]Alexander Kaganov, Paul Chow, Asif Lakhany:
FPGA acceleration of Monte-Carlo based credit derivative pricing. FPL 2008: 329-334 - [c44]Daniel Nunes, Manuel Saldaña, Paul Chow:
A profiler for a heterogeneous multi-core multi-FPGA system. FPT 2008: 113-120 - [c43]Manuel Saldaña, Emanuel Ramalho, Paul Chow:
A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI. ReConFig 2008: 265-270 - [c42]Manuel Saldaña, Arun Patel, Christopher A. Madill, Daniel Nunes, Danyao Wang, Henry Styles, Andrew Putnam, Ralph Wittig, Paul Chow:
MPI as an abstraction for software-hardware interaction for HPRCs. HPRCTA@SC 2008: 1-10 - [e1]Mike Hutton, Paul Chow:
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008. ACM 2008, ISBN 978-1-59593-934-0 [contents] - 2007
- [j11]Lesley Shannon, Paul Chow:
SIMPPL: An Adaptable SoC Framework Using a Programmable Controller IP Interface to Facilitate Design Reuse. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 377-390 (2007) - [j10]Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow:
Routability of Network Topologies in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 15(8): 948-951 (2007) - [c41]Samir Parikh, P. Glenn Gulak, Paul Chow:
A CMOS Image Sensor for DNA Microarrays. CICC 2007: 821-824 - [c40]Sam Lee, Paul Chow:
An FPGA Implementation of Reciprocal Sums for SPME. ERSA 2007: 159-165 - [c39]Paul Chow, Mike Hutton:
Integrating FPGAs in high-performance computing: introduction. FPGA 2007: 131 - [c38]Chichyang Chen, Paul Chow:
Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor. ACM Great Lakes Symposium on VLSI 2007: 540-545 - [c37]Tor M. Aamodt, Paul Chow:
Optimization of data prefetch helper threads with path-expression based statistical modeling. ICS 2007: 210-221 - 2006
- [c36]Arun Patel, Christopher A. Madill, Manuel Saldaña, Chris Comis, Régis Pomès, Paul Chow:
A Scalable FPGA-based Multiprocessor. FCCM 2006: 111-120 - [c35]Manuel Saldaña, Lesley Shannon, Paul Chow:
The routability of multiprocessor network topologies in FPGAs. FPGA 2006: 232 - [c34]Manuel Saldaña, Paul Chow:
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs. FPL 2006: 1-6 - [c33]Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow:
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification. FPL 2006: 1-6 - [c32]Manuel Saldaña, Daniel Nunes, Emanuel Ramalho, Paul Chow:
Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using TMD-MPI. ReConFig 2006: 260-279 - [c31]Manuel Saldaña, Lesley Shannon, Paul Chow:
The routability of multiprocessor network topologies in FPGAs. SLIP 2006: 49-56 - 2005
- [c30]Lesley Shannon, Paul Chow:
Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller. FCCM 2005: 63-72 - [c29]Lesley Shannon, Paul Chow:
Leveraging Reconfigurability in the Design Process. FPL 2005: 731-732 - [c28]Lesley Shannon, Blair Fort, Samir Parikh, Arun Patel, Manuel Saldaña, Paul Chow:
Designing an FPGA SoC Using a Standardized IP Block Interface. FPT 2005: 341-342 - 2004
- [c27]Navid Azizi, Ian Kuon, Aaron Egier, Ahmad Darabiha, Paul Chow:
Reconfigurable Molecular Dynamics Simulator. FCCM 2004: 197-206 - [c26]Lesley Shannon, Paul Chow:
Using reconfigurability to achieve real-time profiling for hardware/software codesign. FPGA 2004: 190-199 - [c25]Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow:
FPGA-based supercomputing: an implementation for molecular dynamics. FPGA 2004: 253 - [c24]Lesley Shannon, Paul Chow:
Maximizing system performance: using reconfigurability to monitor system communications. FPT 2004: 231-238 - [c23]Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen:
Hardware Support for Prescient Instruction Prefetch. HPCA 2004: 84-95 - 2003
- [c22]Lesley Shannon, Paul Chow:
Standardizing the Performance Assessment of Reconfigurable Processor Architectures. FCCM 2003: 282-283 - [c21]Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen:
A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS 2003: 13-24 - 2001
- [c20]Jorge E. Carrillo, Paul Chow:
The effect of reconfigurable units in superscalar processors. FPGA 2001: 141-150 - 2000
- [j9]L. Louis Zhang, Brent Beacham, Massoud R. Hashemi, Paul Chow, Alberto Leon-Garcia:
A Scheduler ASIC for a Programmable Packet Switch. IEEE Micro 20(1): 42-48 (2000) - [c19]Tor M. Aamodt, Paul Chow:
Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. CASES 2000: 128-137
1990 – 1999
- 1999
- [j8]Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic:
The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. Int. J. Parallel Program. 27(5): 327-356 (1999) - [j7]Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja:
The design of an SRAM-based field-programmable gate array. I. Architecture. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 191-197 (1999) - [j6]Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja:
The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 321-330 (1999) - [c18]Ivan Hamer, Paul Chow:
DES Cracking on the Transmogrifier 2a. CHES 1999: 13-24 - [c17]Jeffrey A. Jacob, Paul Chow:
Memory Interfacing and Instruction Specification for Reconfigurable Processors. FPGA 1999: 145-154 - 1998
- [j5]David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow:
The Transmogrifier-2: a 1 million gate rapid-prototyping system. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 188-198 (1998) - 1997
- [c16]David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow:
The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. FPGA 1997: 53-61 - [c15]Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic:
Memory-System Design Considerations for Dynamically-Scheduled Processors. ISCA 1997: 133-143 - [c14]Keith I. Farkas, Paul Chow, Norman P. Jouppi, Zvonko G. Vranesic:
The Multicluster Architecture: Reducing Cycle Time Through Partitioning. MICRO 1997: 149-159 - 1996
- [c13]Mazen A. R. Saghir, Paul Chow, Corinna G. Lee:
Exploiting Dual Data-Memory Banks in Digital Signal Processors. ASPLOS 1996: 234-243 - [c12]David Yeh, Gennady Feygin, Paul Chow:
RACER: a reconfigurable constraint-length 14 Viterbi decoder. FCCM 1996: 60-69 - [c11]Ralph Wittig, Paul Chow:
OneChip: an FPGA processor with reconfigurable logic. FCCM 1996: 126-135 - [c10]Keith I. Farkas, Norman P. Jouppi, Paul Chow:
Register File Design Considerations in Dynamically Scheduled Processors. HPCA 1996: 40-51 - 1995
- [c9]Paul Chow, P. Glenn Gulak:
A Field-Programmable Mixed-Analog-Digital Array. FPGA 1995: 104-109 - [c8]Keith I. Farkas, Norman P. Jouppi, Paul Chow:
How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? HPCA 1995: 78-89 - 1994
- [j4]Gennady Feygin, P. Glenn Gulak, Paul Chow:
Minimizing Excess Code Length and VLSI Complexity in the Multiplication Free Approximation of Arithmetic Coding. Inf. Process. Manag. 30(6): 805-816 (1994) - [c7]Gennady Feygin, P. Glenn Gulak, Paul Chow:
Architectural Advances in the VLSI Implementation of Arithmetic Coding for Binary Image Compression. Data Compression Conference 1994: 254-263 - [c6]Mazen A. R. Saghir, Paul Chow, Corinna G. Lee:
Application-driven design of DSP architectures and compilers. ICASSP (2) 1994: 437-440 - 1993
- [j3]Gennady Feygin, Patrick Glenn Gulak, Paul Chow:
A multiprocessor architecture for Viterbi decoders with linear speedup. IEEE Trans. Signal Process. 41(9): 2907-2917 (1993) - [c5]Gennady Feygin, P. Glenn Gulak, Paul Chow:
Minimizing Error and VLSI Complexity in the Multiplication-Free Approximation of Arithmetic Coding. Data Compression Conference 1993: 118-127 - [c4]Gennady Feygin, Paul Chow, P. Glenn Gulak, John Chappel, Grant Goodes, Oswin Hall, Ahmad Sayes, Satwant Singh, Michael B. Smith, Steven J. E. Wilton:
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback. ISCAS 1993: 1945-1948 - 1991
- [c3]Gennady Feygin, Patrick Glenn Gulak, Paul Chow:
Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up. ICASSP 1991: 1097-1100 - [c2]Michael Takefman, Paul Chow:
A streamlined DSP microprocessor architecture. ICASSP 1991: 1257-1260 - 1990
- [j2]Jonathan Rose, Robert J. Francis, David M. Lewis, Paul Chow:
Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency. IEEE J. Solid State Circuits 25(5): 1217-1225 (1990)
1980 – 1989
- 1987
- [c1]Paul Chow, Mark Horowitz:
Architectural Tradeoffs in the Design of MIPS-X. ISCA 1987: 300-308 - 1983
- [j1]Paul Chow, Zvonko G. Vranesic, Jui Lin Yen:
A Pipelined Distributed Arithmetic PFFT Processor. IEEE Trans. Computers 32(12): 1128-1136 (1983)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2025-01-24 17:14 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
