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ORCIDKaram S. Chatha
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- affiliation: Arizona State University, Tempe, Arizona, USA
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2010 – 2019
- 2014
[j14]Amrit Panda, Karam S. Chatha:
An Embedded Architecture for Energy-Efficient Stream Computing. IEEE Embed. Syst. Lett. 6(3): 57-60 (2014)- [j13]Ran Ginosar, Karam S. Chatha:
Guest Editors' Introduction - Special Issue on Network-on-Chip. IEEE Trans. Computers 63(3): 527-528 (2014) - [c56]Amrit Panda, Karam S. Chatha:
An embedded co-processor architecture for energy-efficient stream computing. ESTIMedia 2014: 60-69 - [e2]Karam S. Chatha, Rolf Ernst, Anand Raghunathan, Ravishankar R. Iyer:
2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2014, Uttar Pradesh, India, October 12-17, 2014. ACM 2014, ISBN 978-1-4503-3050-3 [contents] - 2013
- [j12]Weijia Che, Karam S. Chatha:
Scheduling of synchronous data flow models onto scratchpad memory-based embedded processors. ACM Trans. Embed. Comput. Syst. 13(1s): 30:1-30:25 (2013) - 2012
- [c55]Haeseung Lee, Weijia Che, Karam S. Chatha:
Dynamic scheduling of stream programs on embedded multi-core processors. CODES+ISSS 2012: 93-102 - [c54]Glenn Leary, Weijia Che, Karam S. Chatha:
System-level synthesis of memory architecture for stream processing sub-systems of a MPSoC. DAC 2012: 672-677 - [c53]Weijia Che, Karam S. Chatha:
Unrolling and retiming of stream applications onto embedded multicore processors. DAC 2012: 1272-1277 - 2011
- [j11]Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha:
Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1677-1690 (2011) - [c52]Weijia Che, Karam S. Chatha:
Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming. DAC 2011: 122-127 - [c51]Weijia Che, Karam S. Chatha:
Scheduling of stream programs onto SPM enhanced processors with code overlay. ESTIMedia 2011: 9-18 - [e1]Radu Marculescu, Michael Kishinevsky, Ran Ginosar, Karam S. Chatha:
NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011. ACM/IEEE Computer Society 2011, ISBN 978-1-4503-0720-8 [contents] - 2010
- [c50]Weijia Che, Karam S. Chatha:
Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband Engine. ASAP 2010: 21-28 - [c49]Glenn Leary, Karam S. Chatha:
A holistic approach to network-on-chip synthesis. CODES+ISSS 2010: 213-222 - [c48]Michael A. Baker, Amrit Panda, Nikhil Ghadge, Aniruddha Kadne, Karam S. Chatha:
A performance model and code overlay generator for scratchpad enhanced embedded processors. CODES+ISSS 2010: 287-296 - [c47]Sushu Zhang, Karam S. Chatha:
Thermal aware task sequencing on embedded processors. DAC 2010: 585-590 - [c46]Weijia Che, Amrit Panda, Karam S. Chatha:
Compilation of stream programs for multicore processors that incorporate scratchpad memories. DATE 2010: 1118-1123 - [c45]Weijia Che, Karam S. Chatha:
Scheduling of synchronous data flow models on scratchpad memory based embedded processors. ICCAD 2010: 205-212 - [c44]Michael A. Baker, Karam S. Chatha:
A lightweight run-time scheduler for multitasking multicore stream applications. ICCD 2010: 297-304 - [c43]Glenn Leary, Karam S. Chatha:
Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed Performance. VLSI Design 2010: 200-205
2000 – 2009
- 2009
- [j10]Saraju P. Mohanty, Nasir D. Memon
, Karam S. Chatha:
Circuits and systems for real-time security and copyright protection of multimedia. Comput. Electr. Eng. 35(2): 231-234 (2009) - [j9]Glenn Leary, Krishnan Srinivasan, Krishna Mehta, Karam S. Chatha:
Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique. IEEE Trans. Very Large Scale Integr. Syst. 17(5): 674-687 (2009) - [c42]Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula:
A scalable parallel H.264 decoder on the cell broadband engine architecture. CODES+ISSS 2009: 353-362 - [c41]Glenn Leary, Karam S. Chatha:
Automated technique for design of NoC with minimal communication latency. CODES+ISSS 2009: 471-480 - [c40]Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha:
Throughput optimal task allocation under thermal constraints for multi-core processors. DAC 2009: 776-781 - [c39]Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha:
Performance optimal speed control of multi-core processors under thermal constraints. DATE 2009: 1548-1551 - [c38]Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha:
Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. ICCAD 2009: 310-313 - [c37]Sushu Zhang, Karam S. Chatha, Goran Konjevod:
Near optimal battery-aware energy management. ISLPED 2009: 249-254 - 2008
- [j8]Karam S. Chatha, Krishnan Srinivasan, Goran Konjevod:
Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1425-1438 (2008) - [c36]Sushu Zhang, Karam S. Chatha:
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures. ASP-DAC 2008: 61-66 - [c35]Michael A. Baker, Viswesh Parameswaran, Karam S. Chatha, Baoxin Li:
Power reduction via macroblock prioritization for power aware H.264 video applications. CODES+ISSS 2008: 261-266 - [c34]Sushu Zhang, Karam S. Chatha:
System-level thermal aware design of applications with uncertain execution time. ICCAD 2008: 242-249 - 2007
- [j7]Krishnan Srinivasan, Karam S. Chatha:
Integer linear programming and heuristic techniques for system-level low power scheduling on multiprocessor architectures under throughput constraints. Integr. 40(3): 326-354 (2007) - [j6]Lina Peng, K. Selçuk Candan, Christopher B. Mayer, Karam S. Chatha, Kyung Dong Ryu:
Optimization of media processing workflows with adaptive operator behaviors. Multim. Tools Appl. 33(3): 245-272 (2007) - [j5]Christopher Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan:
ILP and heuristic techniques for system-level design on network processor architectures. ACM Trans. Design Autom. Electr. Syst. 12(4): 48 (2007) - [c33]Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod:
Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms. ASP-DAC 2007: 184-190 - [c32]Christopher Ostler, Karam S. Chatha, Goran Konjevod:
Approximation Algorithm for Process Mapping on Network Processor Architectures. ASP-DAC 2007: 577-582 - [c31]Glenn Leary, Krishna Mehta, Karam S. Chatha:
Performance and resource optimization of NoC router architecture for master and slave IP cores. CODES+ISSS 2007: 155-160 - [c30]Michael A. Baker, Aviral Shrivastava, Karam S. Chatha:
Smart driver for power reduction in next generation bistable electrophoretic display technology. CODES+ISSS 2007: 197-202 - [c29]Christopher Ostler, Karam S. Chatha:
Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures. DAC 2007: 801-804 - [c28]Christopher Ostler, Karam S. Chatha:
An ILP formulation for system-level application mapping on network processor architectures. DATE 2007: 99-104 - [c27]Sushu Zhang, Karam S. Chatha:
Approximation algorithm for the temperature-aware scheduling problem. ICCAD 2007: 281-288 - [c26]Sushu Zhang, Karam S. Chatha, Goran Konjevod:
Approximation algorithms for power minimization of earliest deadline first and rate monotonic schedules. ISLPED 2007: 225-230 - 2006
- [j4]Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod:
Linear-programming-based techniques for synthesis of network-on-chip architectures. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 407-420 (2006) - [c25]Lina Peng, Gisik Kwon, Yinpeng Chen, K. Selçuk Candan, Hari Sundaram, Karam S. Chatha, Maria Luisa Sapino:
Modular Design of Media Retrieval Workflows Using ARIA. CIVR 2006: 491-494 - [c24]Krishnan Srinivasan, Karam S. Chatha:
Layout aware design of mesh based NoC architectures. CODES+ISSS 2006: 136-141 - [c23]Krishnan Srinivasan, Karam S. Chatha:
A low complexity heuristic for design of custom network-on-chip architectures. DATE 2006: 130-135 - [c22]Krishnan Srinivasan, Karam S. Chatha:
A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip Architectures. ISQED 2006: 352-357 - 2005
- [j3]Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha:
Quality-of-service and error control techniques for mesh-based network-on-chip architectures. Integr. 38(3): 353-382 (2005) - [c21]Krishnan Srinivasan, Karam S. Chatha:
SAGA: synthesis technique for guaranteed throughput NoC architectures. ASP-DAC 2005: 489-494 - [c20]Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod:
An automated technique for topology and route generation of application specific on-chip interconnection networks. ICCAD 2005: 231-237 - [c19]Krishnan Srinivasan, Karam S. Chatha:
A technique for low energy mapping and routing in network-on-chip architectures. ISLPED 2005: 387-392 - [c18]Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha:
System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures. ISVLSI 2005: 110-116 - [c17]Lina Peng, Gisik Kwon, K. Selçuk Candan, Kyung Dong Ryu, Karam S. Chatha, Hari Sundaram, Yinpeng Chen:
Media processing workflow design and execution with ARIA. ACM Multimedia 2005: 800-801 - [c16]Nagendran Rangan, Karam S. Chatha:
A Technique for Throughput and Register Optimization during Resource Constrained Pipelined Scheduling. VLSI Design 2005: 564-569 - [c15]Krishnan Srinivasan, Karam S. Chatha:
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis. VLSI Design 2005: 623-628 - 2004
- [c14]Nilanjan Banerjee, Praveen Vellanki, Karam S. Chatha:
A Power and Performance Model for Network-on-Chip Architectures. DATE 2004: 1250-1255 - [c13]Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha:
Quality-of-service and error control techniques for network-on-chip architectures. ACM Great Lakes Symposium on VLSI 2004: 45-50 - [c12]Krishnan Srinivasan, Karam S. Chatha, Goran Konjevod:
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures. ICCD 2004: 422-429 - [c11]Krishnan Srinivasan, Nagender Telkar, Vijay Ramamurthi, Karam S. Chatha:
System-Level Design Techniques for Throughput and Power Optimization of Multiprocessor SoC Architectures. ISVLSI 2004: 39-45 - [c10]Krishnan Srinivasan, Vijay Ramamurthi, Karam S. Chatha:
A Technique for Energy versus Quality of Service Trade-Off for MPEG-2 Decoder. ISVLSI 2004: 313-316 - [c9]K. Selçuk Candan, Lina Peng, Kyung Dong Ryu, Karam S. Chatha, Christopher B. Mayer:
Efficient Stream Routing in Quality- and Resource-Adaptive Flow Architectures. Multimedia Information Systems 2004: 30-39 - [c8]Lina Peng, K. Selçuk Candan, Kyung Dong Ryu, Karam S. Chatha, Hari Sundaram:
ARIA: an adaptive and programmable media-flow architecture for interactive arts. ACM Multimedia 2004: 532-535 - [c7]Krishnan Srinivasan, Karam S. Chatha:
An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures. VLSI Design 2004: 255-260 - 2002
- [j2]Karam S. Chatha, Ranga Vemuri:
Hardware-software partitioning and pipelined scheduling of transformative applications. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 193-208 (2002) - 2001
- [c6]Karam S. Chatha, Ranga Vemuri:
MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs. CODES 2001: 42-47 - 2000
- [j1]Karam S. Chatha, Ranga Vemuri:
An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling. Des. Autom. Embed. Syst. 5(3-4): 281-293 (2000)
1990 – 1999
- 1999
- [c5]Karam S. Chatha, Ranga Vemuri:
Hardware-Software Codesign for Dynamically Reconfigurable Architectures. FPL 1999: 175-184 - [c4]Karam S. Chatha, Ranga Vemuri:
An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems. IEEE International Workshop on Rapid System Prototyping 1999: 134-139 - 1998
- [c3]Karam S. Chatha, Ranga Vemuri:
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. CODES 1998: 139-143 - [c2]Karam S. Chatha, Ranga Vemuri:
A Tool for Partitioning and Pipelined Scheduling of Hardware-Software Systems. ISSS 1998: 145-151 - [c1]Karam S. Chatha, Ranga Vemuri:
Performance Evaluation Tool for Rapid Prototyping of Hardware-Software Codesigns. International Workshop on Rapid System Prototyping 1998: 218-224
Coauthor Index
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