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Jürgen Becker 0001

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affiliation: Karlsruhe Institute of Technology, Germany
affiliation (PhD 1997): Kaiserslautern University of Technology, Germany

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2024
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Marc Neu, Jürgen Becker, Philipp Dorwarth, Torben Ferber, Lea Reuter, Slavomira Stefkova, Kai Lukas Unger:
Real-Time Graph Building on FPGAs for Machine Learning Trigger Applications in Particle Physics. Comput. Softw. Big Sci. 8(1): 8 (2024)
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Jürgen Becker, Marilyn Wolf:
Lynn Conway: Two Remembrances. IEEE Des. Test 41(6): 97-100 (2024)
[j74]
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Konstantinos Balaskas, Heba Khdr, Mohammed Bakr Sikal, Fabian Kreß, Kostas Siozios, Jürgen Becker, Jörg Henkel:
Heterogeneous Accelerator Design for Multi-DNN Workloads via Heuristic Optimization. IEEE Embed. Syst. Lett. 16(4): 317-320 (2024)
[j73]
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Allison McCarn Deiana, Nhan Tran, Joshua Agar, Michaela Blott, Giuseppe Di Guglielmo, Javier M. Duarte, Philip C. Harris, Scott Hauck, Mia Liu, Mark S. Neubauer, Jennifer Ngadiuba, Seda Ogrenci-Memik, Maurizio Pierini, Thea Aarrestad, Steffen Bähr, Jürgen Becker, Anne-Sophie Berthold, Richard J. Bonventre, Tomás E. Müller-Bravo, Markus Diefenthaler, Zhen Dong, Nick Fritzsche, Amir Gholami, Ekaterina Govorkova, Dongning Guo, Kyle J. Hazelwood, Christian Herwig, Babar Khan, Sehoon Kim, Thomas Klijnsma, Yaling Liu, Kin Ho Lo, Tri Nguyen, Gianantonio Pezzullo, Seyedramin Rasoulinezhad, Ryan A. Rivera, Kate Scholberg, Justin Selig, Sougata Sen, Dmitri Strukov, William Tang, Savannah Thais, Kai Lukas Unger, Ricardo Vilalta, Belinavon Krosigk, Shen Wang, Thomas K. Warburton:
Corrigendum: Applications and techniques for fast machine learning in science. Frontiers Big Data 6 (2024)
[c459]
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Annina Gutermann, Jürgen Becker:
A Full-System Approach to Multi-Valued Logic Design: (PhD Forum Paper). ASAP 2024: 226-227
[c458]
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Hosam Alagi, Nikola Fischer, Kai Behrends, Iris Fürst-Walter, Jürgen Becker, Michael Beigl, Franziska Mathis-Ullrich, Björn Hein:
Enhancing Force Sensing Capabilities in Exoskeleton Interfaces Using Compliant Actuator-Sensor Units - A User Study. BioRob 2024: 889-894
[c457]
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Tobias Dörr, Florian Schade, Jürgen Becker, Georgios Keramidas, Nikos Petrellis, Vasilios I. Kelefouras, Michail Mavropoulos, Konstantinos Antonopoulos, Christos P. Antonopoulos, Nikolaos S. Voros, Alexander Ahlbrecht, Wanja Zaeske, Vincent Janson, Phillip Nöldeke, Umut Durak, Christos Panagiotou, Dimitris Karadimas, Nico Adler, Clemens Reichmann, Andreas Sailer, Raphael Weber, Thomas Wilhelm, Wolfgang Gabler, Katrin Weiden, Xavier Anzuela Recasens, Sakir Sezer, Fahad Siddiqui, Rafiullah Khan, Kieran McLaughlin, Sena Yengec Tasdemir, Balmukund Sonigara, Henry Hui, Esther Soriano Viguer, Aridane Álvarez Suárez, Vicente Nicolau Gallego, Manuel Muñoz Alcobendas, Miguel Masmano Tello:
XANDAR: An X-by-Construction Framework for Safety, Security, and Real-Time Behavior of Embedded Software Systems. DATE 2024: 1-6
[c456]
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Patrick Schmidt, Iuliia Topko, Matthias Stammler, Tanja Harbaum, Jürgen Becker, Rico Berner, Omar Ahmed, Jakub Jagielski, Thomas Seidler, Markus Abel, Marius Kreutzer, Maximilian Kirschner, Victor Pazmino Betancourt, Robin Sehm, Lukas Groth, Andrija Neskovic, Rolf Meyer, Saleh Mulhem, Mladen Berekovic, Matthias Probst, Manuel Brosch, Georg Sigl, Thomas Wild, Matthias Ernst, Andreas Herkersdorf, Florian Aigner, Stefan Hommes, Sebastian Lauer, Maximilian Seidler, Thomas Raste, Gasper Skvarc Bozic, Ibai Irigoyen Ceberio, Muhammad Hassan, Albrecht Mayer:
EMDRIVE Architecture: Embedded Distributed Computing and Diagnostics from Sensor to Edge. DATE 2024: 1-6
[c455]
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Matthias Stammler, Julian Lorenz, Eric Sax, Jürgen Becker, Matthias Hamann, Patrick Bidinger, Andreas Dewald, Paraskevi Georgouti, Alexios Camarinopoulos, Günter Becker, Klaus Finsterbusch, Maximilian Kirschner, Laurenz Adolph, Carl Philipp Hohl, Maria Rill, Daniel Vonderau, Victor Pazmino Betancourt:
UNCOVER: Data-Driven Design Support through Continuous Monitoring of Security Incidents. DATE 2024: 1-6
[c454]
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Julian Höfer, Matthias Stammler, Fabian Kreß, Tim Hotfilter, Tanja Harbaum, Jürgen Becker:
BayWatch: Leveraging Bayesian Neural Networks for Hardware Fault Tolerance and Monitoring. DFT 2024: 1-6
[c453]
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Matthias Stammler, Florian Schade, Jürgen Becker:
Automated Polyhedron-based TDMA Schedule Design for Predictable Mixed-Criticality MPSoCs. DSD 2024: 403-409
[c452]
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Patrick Schmidt, Jürgen Becker:
Ph.D. Project: Compiler-Driven Hardware/Software Co- Design for Embedded AI. FCCM 2024: 241-242
[c451]
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Fabian Kreß, Vladimir Sidorenko, Iuliia Topko, Kai Lukas Unger, Tanja Harbaum, Jürgen Becker:
VHDL Crash Course: A Multimedia-Based Teaching Approach. GeCon 2024: 1-6
[c450]
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Fabian Lesniak, Annina Gutermann, Tanja Harbaum, Jürgen Becker:
Enhanced Accelerator Design for Efficient CNN Processing with Improved Row-Stationary Dataflow. ACM Great Lakes Symposium on VLSI 2024: 151-157
[c449]
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Oliver Oey, Michael Hübner, Timo Stripf, Jürgen Becker:
Embedded Multi-Core Code Generation with Cross-Layer Parallelization. PARMA-DITAM 2024: 5:1-5:13
[c448]
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Marius Kreutzer, Maximilian Seidler, Konstantin Dudzik, Victor Pazmino Betancourt, Jürgen Becker:
Migration of Isolated Application Across Heterogeneous Edge Systems. ICFEC 2024: 64-70
[c447]
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Jann Krausse, Sven Nitzsche, Brian Pachideh, Carmen Weigelt, Klaus Knobloch, Jürgen Becker:
Exploring Neuronal Leakage for Spiking Neural Networks on Event-Driven Hardware. ICONS 2024: 140-147
[c446]
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Jürgen Becker, Zhenman Fang, Viktor K. Prasanna, Marco D. Santambrogio, Ramachandran Vaidyanathan:
31st Reconfigurable Architectures Workshop (RAW 2024). IPDPS (Workshops) 2024: 79
[c445]
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Julian Höfer, Michael Gauß, Manuela Adams, Fabian Kreß, Fabian Kempf, Christian Maximilian Karle, Tanja Harbaum, Andreas Barth, Jürgen Becker:
A Challenge-Based Blended Learning Approach for an Introductory Digital Circuits and Systems Course. ISCAS 2024: 1-5
[c444]
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Fabian Kreß, El Mahdi El Annabi, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker:
Automated Deep Neural Network Inference Partitioning for Distributed Embedded Systems. ISVLSI 2024: 39-44
[c443]
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Matthias Stammler, Julian Höfer, Patrick Schmidt, Tanja Harbaum, Jürgen Becker:
ICE TEA: Insertion of Custom Early Exits for Time-, Energy- & Anomaly-Aware Neural Networks. ISVLSI 2024: 656-660
[c442]
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Himanshu Thapliyal, Jürgen Becker:
Message from the General Chairs; ISVLSI 2024. ISVLSI 2024: xxvi-xxvii
[c441]
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Shaown Mojumder, Simon Friedrich, Emil Matús, Gerhard P. Fettweis, Matthias Lüders, Martin Friedrich, Oliver Renke, Holger Blume, Julian Höfer, Patrick Schmidt, Jürgen Becker, Darius Grantz, Markus Kock, Jens Benndorf, Nael Fasfous, Pierpaolo Morì, Hans-Jörg Vögel, Samira Ahmadifarsani, Leonidas Kontopoulos, Ulf Schlichtmann, Kay Bierzynski:
ZuSE-KI-Mobil AI Chip Design Platform: An Overview. NorCAS 2024: 1-7
[c440]
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Iuliia Topko, Tanja Harbaum, Jürgen Becker:
Towards a General Compilation Approach for On-device Training in Embedded Systems. NorCAS 2024: 1-7
[c439]
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Konstantin Dudzik, Maximilian Kirschner, Victor Pazmino Betancourt, Jürgen Becker:
Work in Progress: Predictable Execution of Isolated Real-Time Tasks on Multicore Systems Using the LET Paradigm. RTAS 2024: 386-389
[c438]
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Alexey Serdyuk, Fabian Kreß, Iuliia Topko, Tanja Harbaum, Jürgen Becker, Tim Hamann, Peter Kämpf:
Improving Online Handwriting Trajectory Reconstruction Based on Temporal Convolutional Networks. SDF 2024: 1-8
[c437]
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Christian Maximilian Karle, Marc Neu, Benjamin Nuss, Jiayi Chen, Lukas Witte, Andre Scheder, Tanja Harbaum, Jürgen Becker:
Modular Hardware Design for High-Performance MIMO-Capable SDR Systems to Accelerate 6G Development. SOCC 2024: 1-6
[c436]
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Christian Maximilian Karle, Marc Neu, Benjamin Nuss, Lukas Witte, Andre Scheder, Eva Waldner, Ema Shkurtaj, Tanja Harbaum, Jürgen Becker:
Scalable Multi-Level Synchronization Technique of Distributed Multi-RFSoC-Server Systems for 6G. SOCC 2024: 1-6
[c435]
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Jann Krausse, Moritz Neher, Iris Fürst-Walter, Carmen Weigelt, Tanja Harbaum, Klaus Knobloch, Jürgen Becker:
On Metric-Driven Development of Embedded Neuromorphic AI. SOCC 2024: 1-6
[c434]
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Marc Neu, Christian Maximilian Karle, Patrick Schmidt, Julian Höfer, Tanja Harbaum, Jürgen Becker:
A Dynamically Pipelined Dataflow Architecture for Graph Convolutions in Real-Time Event Interpretation. SOCC 2024: 1-6
[c433]
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Patrick Schmidt, Johannes Pfau, Tim Hotfilter, Matthias Stammler, Tanja Harbaum, Jürgen Becker:
RVVe: A Minimal RISC-V Vector Processor for Embedded AI Acceleration. SOCC 2024: 1-6
[c432]
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Fabian Kreß, Alexey Serdyuk, Denis Kobsar, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker:
LOTTA: An FPGA-based Low-Power Temporal Convolutional Network Hardware Accelerator. SOCC 2024: 126-131
[i14]
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  - journals/corr/abs-2406-19913
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Fabian Kreß, El Mahdi El Annabi, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker:
Automated Deep Neural Network Inference Partitioning for Distributed Embedded Systems. CoRR abs/2406.19913 (2024)
[i13]
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Alexandru Vasilache, Sven Nitzsche, Daniel Flögel, Tobias Schürmann, Stefan von Dosky, Thomas Bierweiler, Marvin Mußler, Florian Kälber, Sören Hohmann, Jürgen Becker:
Low-Power Vibration-Based Predictive Maintenance for Industry 4.0 using Neural Networks: A Survey. CoRR abs/2408.00516 (2024)
[i12]
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Alexandru Vasilache, Jann Krausse, Klaus Knobloch, Jürgen Becker:
Hybrid Spiking Neural Networks for Low-Power Intra-Cortical Brain-Machine Interfaces. CoRR abs/2409.04428 (2024)
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Maximilian Kirschner, Konstantin Dudzik, Jürgen Becker:
Work-in-Progress: Real-Time Neural Network Inference on a Custom RISC-V Multicore Vector Processor. CoRR abs/2410.10340 (2024)
2023
[j72]
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Fabian Kreß, Vladimir Sidorenko, Patrick Schmidt, Julian Höfer, Tim Hotfilter, Iris Walter, Tanja Harbaum, Jürgen Becker:
CNNParted: An open source framework for efficient Convolutional Neural Network inference partitioning in embedded systems. Comput. Networks 229: 109759 (2023)
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Tim Hotfilter, Julian Höfer, Fabian Kreß, Fabian Kempf, Leonhard Kraft, Tanja Harbaum, Jürgen Becker:
A Hardware-Centric Approach to Increase and Prune Regular Activation Sparsity in CNNs. AICAS 2023: 1-5
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Kai Lukas Unger, Jürgen Becker, Christian Kiesling, Yichuan Ma, Felix Meggendorfer, Marc Neu, Elia Schmidt, Ulrike Zweigart:
A Convolution Neural Network Based Displaced Vertex Trigger for the Belle II Experiment. ARC 2023: 173-184
[c429]
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Maximilian Kirschner, Federico Nicolás Peccia, Felix Thömmes, Victor Pazmino Betancourt, Oliver Bringmann, Jürgen Becker:
Characterization of Execution Time Variability in FPGA-Based AI-Accelerators. DASC/PiCom/CBDCom/CyberSciTech 2023: 1-8
[c428]
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Fabian Kempf, Julian Höfer, Tanja Harbaum, Jürgen Becker, Nael Fasfous, Alexander Frickenstein, Hans-Jörg Vögel, Simon Friedrich, Robert Wittig, Emil Matús, Gerhard P. Fettweis, Matthias Lüders, Holger Blume, Jens Benndorf, Darius Grantz, Martin Zeller, Dietmar Engelke, Karl-Heinz Eickel:
The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective. DATE 2023: 1-6
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Marc Neu, Christian Maximilian Karle, Benjamin Nuss, Patrick Gröschel, Jürgen Becker:
A Scalable and Cost-Efficient Antenna Testbed Using FPGA-Server Compound Structures for Prototyping 6G Applications. DCOSS-IoT 2023: 171-178
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Florian Schade, Tobias Dörr, Alexander Ahlbrecht, Vincent Janson, Umut Durak, Jürgen Becker:
Automatic Deployment of Embedded Real-Time Software Systems to Hypervisor-Managed Platforms. DSD 2023: 436-443
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Matthias Stammler, Matthias Hamann, Tanja Harbaum, Jürgen Becker:
Mitigating Masking in Automotive Communication Systems: Modeling and Hardware Generation. DSD 2023: 561-568
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Fabian Kreß, Alexey Serdyuk, Micha Hiegle, Disnebio Waldmann, Tim Hotfilter, Julian Höfer, Tim Hamann, Jens Barth, Peter Kämpf, Tanja Harbaum, Jürgen Becker:
ATLAS: An Approximate Time-Series LSTM Accelerator for Low-Power IoT Applications. DSD 2023: 569-576
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Marius Kreutzer, Maximilian Seidler, Victor Pazmino Betancourt, Jürgen Becker:
Work-in-Progress: Integrating WebAssembly into Service-Oriented Architectures for Edge Systems. EMSOFT 2023: 17-18
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Anqi Chu, Chris Manuel Hermann, Johannes Silz, Johannes Pfau, Kevin Muñoz Barón, Nidhi Anantharajaiah, Patrick Schmidt, Tim Hotfilter, Xiang Xie, Jürgen Becker, Ingmar Kallfass, Jörg Roth-Stielow, Wilhelm Stork:
LETSCOPE: Lifecycle Extensions Through Software-Defined Predictive Control of Power Electronics. EUROCON 2023: 665-670
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Christian Maximilian Karle, Marc Neu, Johannes Pfau, Jan Sperling, Jürgen Becker:
ReLoDAQ: Resource-Efficient, Low-Overhead 200 Gbits^-1 Data Acquisition System for 6G Prototyping. FCCM 2023: 209
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Julian Höfer, Fabian Kempf, Tim Hotfilter, Fabian Kreß, Tanja Harbaum, Jürgen Becker:
SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators. ACM Great Lakes Symposium on VLSI 2023: 287-292
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Fabian Lesniak, Nidhi Anantharajaiah, Tanja Harbaum, Jürgen Becker:
Non-Intrusive Runtime Monitoring for Manycore Prototypes. DroneSE/RAPIDO@HiPEAC 2023: 31-38
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Tim Hotfilter, Patrick Schmidt, Julian Höfer, Fabian Kreß, Tanja Harbaum, Jürgen Becker:
An Analytical Model of Configurable Systolic Arrays to find the Best-Fitting Accelerator for a given DNN Workload. DroneSE/RAPIDO@HiPEAC 2023: 73-78
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Julian Höfer, Tim Hotfilter, Fabian Kreß, Chen Qiu, Tanja Harbaum, Jürgen Becker:
A Hardware-Aware Sampling Parameter Search for Efficient Probabilistic Object Detection. ICVS 2023: 299-309
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Matthias Stammler, Julian Höfer, David Kraus, Patrick Schmidt, Tim Hotfilter, Tanja Harbaum, Jürgen Becker:
EFFECT: An End-to-End Framework for Evaluating Strategies for Parallel AI Anomaly Detection. INNS DLIA@IJCNN 2023: 499-508
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Victor Pazmino Betancourt, Maximilian Kirschner, Marius Kreutzer, Jürgen Becker:
Policy Model for Task Reallocation at Runtime in Edge Computing Infrastructures. IoTaIS 2023: 45-51
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Iris Fürst-Walter, Antonio Nappi, Tanja Harbaum, Jürgen Becker:
Design Space Exploration on Efficient and Accurate Human Pose Estimation from Sparse IMU-Sensing. IROS 2023: 10888-10893
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Victor Pazmino Betancourt, Maximilian Kirschner, Marius Kreutzer, Jürgen Becker:
Policy-Based Task Allocation at Runtime for a Self-Adaptive Edge Computing Infrastructure. ISADS 2023: 1-8
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Tobias Fleck, Svetlana Pavlitska, Sven Nitzsche, Brian Pachideh, Federico Nicolás Peccia, Soikat Hasan Ahmed, Svea Marie Meyer, Mathis Richter, Kevin Broertjes, Emre Neftci, Jürgen Becker, Oliver Bringmann, J. Marius Zöllner:
Low-Power Traffic Surveillance using Multiple RGB and Event Cameras: A Survey. ISC2 2023: 1-7
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Johannes Pfau, Richard Leys, Marc Neu, Alexey Serdyuk, Ivan Peric, Jürgen Becker:
A Unified SoC Lab Course: Combined Teaching of Mixed Signal Aspects, System Integration, Software Development and Documentation. ISCAS 2023: 1-5
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Nidhi Anantharajaiah, Yunhe Xu, Fabian Lesniak, Tanja Harbaum, Jürgen Becker:
DREAM: Distributed Reinforcement Learning Enabled Adaptive Mixed-Critical NoC. ISVLSI 2023: 1-6
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Nidhi Anantharajaiah, Fabian Lesniak, Tanja Harbaum, Jürgen Becker:
Reinforcement Learning Enabled Multi-Layered NoC for Mixed Criticality Systems. MCSoC 2023: 38-44
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Matthias Stammler, Vladimir Sidorenko, Fabian Kreß, Patrick Schmidt, Jürgen Becker:
Context-Aware Layer Scheduling for Seamless Neural Network Inference in Cloud-Edge Systems. MCSoC 2023: 97-104
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Fabian Kempf, Julian Höfer, Tim Hotfilter, Jürgen Becker:
A Low-Stall Methodology for an Interleaved Processor State Replication. MCSoC 2023: 276-283
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Fabian Lesniak, Tanja Harbaum, Jürgen Becker:
Low-latency inter-domain communication on the Xen hypervisor. MCSoC 2023: 340-346
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Jürgen Becker:
Embedded reliable HPC Integration enabling smart Automotive & IoT Systems. MECO 2023: 1
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Fabian Kempf, Jürgen Becker:
Leveraging Adaptive Redundancy in Multi-Core Processors for Realizing Adaptive Fault Tolerance in Mixed-Criticality Systems. MECO 2023: 1-5
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Matthias Stammler, Matthias Hamann, Jürgen Becker:
Multilevel Security Model for Secure Information Flow Inside Software Components Employing Automated Code Generation. MECO 2023: 1-6
[c402]
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Fabian Kreß, Johannes Pfau, Fabian Kempf, Patrick Schmidt, Zhuofan He, Tanja Harbaum, Jürgen Becker:
Automated Replacement of State-Holding Flip-Flops to Enable Non-Volatile Checkpointing. NorCAS 2023: 1-7
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Johannes Pfau, Jiro Hernandez, Maximilian Reuter, Klaus Hofmann, Jürgen Becker:
Co-Simulating Region-Based Dynamic Voltage Scaling for FPGA Architecture Design. NorCAS 2023: 1-7
[c400]
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Tobias Dörr, Florian Schade, Jürgen Becker:
Pattern-Based Information Flow Control for Safety-Critical On-Chip Systems. SAFECOMP 2023: 181-195
[c399]
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Daniel Hofman, Mario Brcic, Mihael Kovac, Tim Hotfilter, Jürgen Becker, Dominik Reinhardt, Sorin Mihai Grigorescu, R. Stevens, T. T. Vo:
European Processor Initiative Demonstration of Integrated Semi-Autonomous Driving System. SOCC 2023: 1-6
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Tim Hotfilter, Julian Höfer, Philipp Merz, Fabian Kreß, Fabian Kempf, Tanja Harbaum, Jürgen Becker:
Leveraging Mixed-Precision CNN Inference for Increased Robustness and Energy Efficiency. SOCC 2023: 1-6
[c397]
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Fabian Lesniak, Tanja Harbaum, Jürgen Becker:
Approximate Accelerators: A Case Study using Runtime Reconfigurable Processors. SOCC 2023: 1-6
[c396]
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Brian Pachideh, Christian Zielke, Sven Nitzsche, Jürgen Becker:
Towards Hardware-Software Self-Adaptive Acceleration of Spiking Neural Networks on Reconfigurable Digital Hardware. SOCC 2023: 1-6
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Alexey Serdyuk, Fabian Kreß, Micha Hiegle, Tanja Harbaum, Jürgen Becker, Florent Imbert, Yann Soullard, Romain Tavenard, Éric Anquetil, Jens Barth, Peter Kämpf:
Towards the on-device Handwriting Trajectory Reconstruction of the Sensor Enhanced Pen. WF-IoT 2023: 1-6
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Jürgen Becker, Andrew Marshall, Tanja Harbaum, Amlan Ganguly, Fahad Siddiqui, Kieran McLaughlin:
36th IEEE International System-on-Chip Conference, SOCC 2023, Santa Clara, CA, USA, September 5-8, 2023. IEEE 2023, ISBN 979-8-3503-0011-6 [contents]
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Iris Fürst-Walter, Antonio Nappi, Tanja Harbaum, Jürgen Becker:
Design Space Exploration on Efficient and Accurate Human Pose Estimation from Sparse IMU-Sensing. CoRR abs/2308.02397 (2023)
2022
[j71]
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Houssem Guissouma, Carl Philipp Hohl, Fabian Lesniak, Marc Schindewolf, Jürgen Becker, Eric Sax:
Lifecycle Management of Automotive Safety-Critical Over the Air Updates: A Systems Approach. IEEE Access 10: 57696-57717 (2022)
[j70]
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Allison McCarn Deiana, Nhan Tran, Joshua Agar, Michaela Blott, Giuseppe Di Guglielmo, Javier M. Duarte, Philip C. Harris, Scott Hauck, Mia Liu, Mark S. Neubauer, Jennifer Ngadiuba, Seda Ogrenci Memik, Maurizio Pierini, Thea Aarrestad, Steffen Bähr, Jürgen Becker, Anne-Sophie Berthold, Richard J. Bonventre, Tomás E. Müller-Bravo, Markus Diefenthaler, Zhen Dong, Nick Fritzsche, Amir Gholami, Ekaterina Govorkova, Dongning Guo, Kyle J. Hazelwood, Christian Herwig, Babar Khan, Sehoon Kim, Thomas Klijnsma, Yaling Liu, Kin Ho Lo, Tri Nguyen, Gianantonio Pezzullo, Seyedramin Rasoulinezhad, Ryan A. Rivera, Kate Scholberg, Justin Selig, Sougata Sen, Dmitri Strukov, William Tang, Savannah Thais, Kai Lukas Unger, Ricardo Vilalta, Belinavon Krosigk, Shen Wang, Thomas K. Warburton:
Applications and Techniques for Fast Machine Learning in Science. Frontiers Big Data 5: 787421 (2022)
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Jessé Barreto de Barros, Nidhi Anantharajaiah, Mauricio Ayala-Rincón, Carlos Humberto Llanos Quintero, Jürgen Becker:
The impact of formulation of cost function in Task Mapping Problem on NoCs using bio-inspired based-metaheuristics. Microprocess. Microsystems 94: 104668 (2022)
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Johannes Pfau, Peter Wagih Zaki, Jürgen Becker:
V-FPGAs: Increasing Performance with Manual Placement, Timing Extraction and Extended Timing Modeling. J. Signal Process. Syst. 94(9): 865-882 (2022)
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Leonard Masing, Tobias Dörr, Florian Schade, Jürgen Becker, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Efstratios Tiganourias, Vasilios I. Kelefouras, Konstantinos Antonopoulos, Nikos S. Voros, Umut Durak, Alexander Ahlbrecht, Wanja Zaeske, Christos Panagiotou, Dimitris Karadimas, Nico Adler, Andreas Sailer, Raphael Weber, Thomas Wilhelm, Géza Németh, Fahad Siddiqui, Rafiullah Khan, Vahid Garousi, Sakir Sezer, Victor Morales:
XANDAR: Exploiting the X-by-Construction Paradigm in Model-based Development of Safety-critical Systems. DATE 2022: 1-5
[c393]
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Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Driton Salihu, Julian Höfer, Anmol Singh, Naveen Shankar Nagaraja, Hans-Jörg Vögel, Nguyen Anh Vu Doan, Maurizio Martina, Jürgen Becker, Walter Stechele:
AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms. DATE 2022: 238-243
[c392]
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Tim Hotfilter, Fabian Kreß, Fabian Kempf, Jürgen Becker, Juan Miguel De Haro Ruiz, Daniel Jiménez-González, Miquel Moretó, Carlos Álvarez, Jesús Labarta, Imen Baili:
Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs. DATE 2022: 628-631
[c391]
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Fabian Kreß, Julian Höfer, Tim Hotfilter, Iris Walter, Vladimir Sidorenko, Tanja Harbaum, Jürgen Becker:
Hardware-aware Partitioning of Convolutional Neural Network Inference for Embedded AI Applications. DCOSS 2022: 133-140
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Nidhi Anantharajaiah, Jürgen Becker:
Adaptive Exploration Based Routing for Spatial Isolation in Mixed Criticality Systems. DSD 2022: 174-180
[c389]
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Timo Sandmann, Jürgen Becker:
Hardware Support for Predictable Resource Sharing in Virtualized Heterogeneous Multicores. DSD 2022: 189-196
[c388]
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Fabian Kempf, Christoph Kühbacher, Christian Mellwig, Sebastian Altmeyer, Theo Ungerer, Jürgen Becker:
A holistic hardware-software approach for fault-aware embedded systems. DSD 2022: 704-711
[c387]
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Tobias Dörr, Florian Schade, Alexander Ahlbrecht, Wanja Zaeske, Leonard Masing, Umut Durak, Jürgen Becker:
A Behavior Specification and Simulation Methodology for Embedded Real-Time Software. DS-RT 2022: 151-159
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Christian Maximilian Karle, Marius Kreutzer, Johannes Pfau, Jürgen Becker:
A hardware/software co-design approach to prototype 6G mobile applications inside the GNU Radio SDR Ecosystem using FPGA hardware accelerators. HEART 2022: 33-41
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Valentin Kiechle, Matthias Börsig, Sven Nitzsche, Ingmar Baumgart, Jürgen Becker:
PREUNN: Protocol Reverse Engineering using Neural Networks. ICISSP 2022: 345-356
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Jürgen Becker, Lana Josipovic, Viktor K. Prasanna, Marco D. Santambrogio, Ramachandran Vaidyanathan:
29th Reconfigurable Architectures Workshop (RAW 2022). IPDPS Workshops 2022: 65-66
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Tobias Dörr, Florian Schade, Leonard Masing, Jürgen Becker, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Vasilios I. Kelefouras, Nikolaos S. Voros:
Safety by Construction: Pattern-Based Application of Safety Mechanisms in XANDAR. ISVLSI 2022: 369-370
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Tim Hotfilter, Fabian Kreß, Fabian Kempf, Jürgen Becker, Imen Baili:
Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA. ISVLSI 2022: 371-372
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Fabian Kreß, Alexey Serdyuk, Tim Hotfilter, Julian Höfer, Tanja Harbaum, Jürgen Becker, Tim Hamann:
Hardware-aware Workload Distribution for AI-based Online Handwriting Recognition in a Sensor Pen. MECO 2022: 1-4
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Fabian Kreß, Julian Höfer, Tim Hotfilter, Iris Walter, El Mahdi El Annabi, Tanja Harbaum, Jürgen Becker:
Automated Search for Deep Neural Network Inference Partitioning on Embedded FPGA. PKDD/ECML Workshops (1) 2022: 557-568
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Florian Schade, Timo Sandmann, Jürgen Becker, Henrik Theiling:
Using Trace Data for Run-Time Optimization of Parallel Execution in Real-Time Multi-Core Systems. RTCSA 2022: 228-234
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Fabian Kempf, Julian Höfer, Fabian Kreß, Tim Hotfilter, Tanja Harbaum, Jürgen Becker:
Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors. SOCC 2022: 1-6
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Florian Schade, Tobias Dörr, Jürgen Becker:
Hypervisor-Based Target Deployment Strategies for Time Predictability in Model-Based Development. SOCC 2022: 1-2
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Fahad Siddiqui, Rafiullah Khan, Sakir Sezer, Kieran McLaughlin, Leonard Masing, Tobias Dörr, Florian Schade, Jürgen Becker, Alexander Ahlbrecht, Wanja Zaeske, Umut Durak, Nico Adler, Andreas Sailer, Raphael Weber, Thomas Wilhelm, Géza Németh, Victor Morales, Paco Gomez, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Vasilios I. Kelefouras, Konstantinos Antonopoulos, Nikolaos S. Voros, Christos Panagiotou, Dimitris Karadimas:
XANDAR: A holistic Cybersecurity Engineering Process for Safety-critical and Cyber-physical Systems. VTC Spring 2022: 1-5
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Sakir Sezer, Thomas Büchner, Jürgen Becker, Andrew Marshall, Fahad Siddiqui, Tanja Harbaum, Kieran McLaughlin:
35th IEEE International System-on-Chip Conference, SOCC 2022, Belfast, United Kingdom, September 5-8, 2022. IEEE 2022, ISBN 978-1-6654-5985-3 [contents]
2021
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Leonard Masing, Fabian Lesniak, Jürgen Becker:
A Hybrid Prototyping Framework in a Virtual Platform Centered Design and Verification Flow. IEEE Embed. Syst. Lett. 13(1): 1-4 (2021)
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Tobias Dörr, Timo Sandmann, Jürgen Becker:
Model-based configuration of access protection units for multicore processors in embedded systems. Microprocess. Microsystems 87: 104377 (2021)
[j65]
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Tobias Dörr, Timo Sandmann, Patrick Friederich, Arnd Leitner, Jürgen Becker:
Achieving cost-efficient fail-operational behavior based on inherent redundancy at the system level. Microprocess. Microsystems 87: 104380 (2021)
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André B. Perina, Arthur Silitonga, Jürgen Becker, Vanderlei Bonato:
Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis. IEEE Trans. Computers 70(12): 2070-2082 (2021)
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Maximilian Reuter, Johannes Pfau, Tillmann A. Krauss, Jürgen Becker, Klaus Hofmann:
From MOSFETs to Ambipolar Transistors: Standard Cell Synthesis for the Planar RFET Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 114-125 (2021)
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Nadir Khan, Sven Nitzsche, Asier Garciandia López, Jürgen Becker:
Utilizing and Extending Trusted Execution Environment in Heterogeneous SoCs for a Pay-Per-Device IP Licensing Scheme. IEEE Trans. Inf. Forensics Secur. 16: 2548-2563 (2021)
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Nadir Khan, Jorge Castro-Godínez, Shixiang Xue, Jörg Henkel, Jürgen Becker:
Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 38-50 (2021)
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Johannes Pfau, Peter Wagih Zaki, Jürgen Becker:
Evaluation of Different Manual Placement Strategies to Ensure Uniformity of the V-FPGA. ARC 2021: 35-49
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Nidhi Anantharajaiah, Zhe Zhang, Jürgen Becker:
Multi-layered NoCs with Adaptive Routing for Mixed Criticality Systems. ARC 2021: 125-139
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Nadir Khan, Benjamin Hettwer, Jürgen Becker:
Moving Target and Implementation Diversity Based Countermeasures Against Side-Channel Attacks. ARC 2021: 188-202
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Fabian Lesniak, Fabian Kreß, Jürgen Becker:
Transparent Near-Memory Computing with a Reconfigurable Processor. ARC 2021: 221-231
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Tobias Dörr, Timo Sandmann, Hannes Mohr, Jürgen Becker:
Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board Networks. DSD 2021: 107-114
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Jürgen Becker, Leonard Masing, Tobias Dörr, Florian Schade, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Efstratios Tiganourias, Vasilios I. Kelefouras, Konstantinos Antonopoulos, Nikolaos S. Voros, Umut Durak, Alexander Ahlbrecht, Wanja Zaeske, Christos Panagiotou, Dimitris Karadimas, Nico Adler, Andreas Sailer, Raphael Weber, Thomas Wilhelm, Florian Oszwald, Dominik Reinhardt, Mohamad Chamas, Adnan Bekan, Graham Smethurst, Fahad Siddiqui, Rafiullah Khan, Vahid Garousi, Sakir Sezer, Victor Morales:
XANDAR: X-by-Construction Design framework for Engineering Autonomous & Distributed Real-time Embedded Software Systems. FPL 2021: 382-383
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Sven Nitzsche, Brian Pachideh, Victor Pazmino Betancourt, Norbert Link, Christoph Schauer, Lukas Theurer, Valentin Haas, Philipp Marquardt, Sergey Biniaminov, Jürgen Becker:
Neuromorphic Vision mit Spiking Neural Networks zur Sturzerkennung im betreuten Wohnen. GI-Jahrestagung 2021: 1247-1253
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Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Mohamed Badawy, Felix Hundhausen, Julian Höfer, Naveen Shankar Nagaraja, Christian Unger, Hans-Jörg Vögel, Jürgen Becker, Tamim Asfour, Walter Stechele:
Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands. ICRA 2021: 13430-13437
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Victor Pazmino Betancourt, Bo Liu, Jürgen Becker:
Towards Policy-based Task Self-Reallocation in Dynamic Edge Computing Systems. INDIN 2021: 1-6
[c366]
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Matthias Kern, Bo Liu, Victor Pazmino Betancourt, Jürgen Becker:
Model-based Attack Tree Generation for Cybersecurity Risk-Assessments in Automotive. ISSE 2021: 1-7
[c365]
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Kevin Neubauer, Marcel Rumez, Huiying Tremmel, Augusto W. Hoppe, Reiner Kriesten, Philipp Nenninger, Eric Sax, Jürgen Becker:
Virtual Verification of E/E Architectures for Secure Automated Driving Functions. ISSE 2021: 1-8
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Fabian Kempf, Thomas Hartmann, Steffen Baehr, Jürgen Becker:
An Adaptive Lockstep Architecture for Mixed-Criticality Systems. ISVLSI 2021: 7-12
[c363]
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Augusto W. Hoppe, Jürgen Becker, Fernanda Lima Kastensmidt:
High-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring. LASCAS 2021: 1-4
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Iris Walter, Jonas Ney, Tim Hotfilter, Vladimir Rybalkin, Julian Höfer, Norbert Wehn, Jürgen Becker:
Embedded Face Recognition for Personalized Services in the Assistive Robotics. PKDD/ECML Workshops (1) 2021: 339-350
[c361]
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Sven Nitzsche, Moritz Neher, Stefan von Dosky, Jürgen Becker:
Ultra-low Power Machinery Fault Detection Using Deep Neural Networks. PKDD/ECML Workshops (1) 2021: 390-396
[c360]
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Kevin Neubauer, Leonard Masing, Michael Mahl, Jürgen Becker, Max E. Kramer, Clemens Reichmann:
Template-Driven and Hardware-Centric Cross-Domain E/E Architecture Simulation. RSP 2021: 29-35
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Tim Hotfilter, Julian Höfer, Fabian Kreß, Fabian Kempf, Jürgen Becker:
FLECSim-SoC: A Flexible End-to-End Co-Design Simulation Framework for System on Chips. SoCC 2021: 83-88
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Nidhi Anantharajaiah, Felix Knopf, Jürgen Becker:
Ant Colony Optimization Based NoCs for Flexible Spatial Isolation in Mixed Criticality Systems. SoCC 2021: 248-253
[c357]
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Florian Schade, David Barton, Jürgen Fleischer, Jürgen Becker:
Evaluation of a Hypervisor-Based Smart Controller for Industry 4.0 Functions in Manufacturing. WF-IoT 2021: 680-685
[i9]
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Allison McCarn Deiana, Nhan Tran, Joshua Agar, Michaela Blott, Giuseppe Di Guglielmo, Javier M. Duarte, Philip C. Harris, Scott Hauck, Mia Liu, Mark S. Neubauer, Jennifer Ngadiuba, Seda Ogrenci Memik, Maurizio Pierini, Thea Aarrestad, Steffen Bähr, Jürgen Becker, Anne-Sophie Berthold, Richard J. Bonventre, Tomás E. Müller-Bravo, Markus Diefenthaler, Zhen Dong, Nick Fritzsche, Amir Gholami, Ekaterina Govorkova, Kyle J. Hazelwood, Christian Herwig, Babar Khan, Sehoon Kim, Thomas Klijnsma, Yaling Liu, Kin Ho Lo, Tri Nguyen, Gianantonio Pezzullo, Seyedramin Rasoulinezhad, Ryan A. Rivera, Kate Scholberg, Justin Selig, Sougata Sen, Dmitri Strukov, William Tang, Savannah Thais, Kai Lukas Unger, Ricardo Vilalta, Belinavon Krosigk, Thomas K. Warburton, Maria Acosta Flechas, Anthony Aportela, Thomas Calvet, Leonardo Cristella, Daniel Diaz, Caterina Doglioni, Maria Domenica Galati, Elham E Khoda, Farah Fahim, Davide Giri, Benjamin Hawks, Duc Hoang, Burt Holzman, Shih-Chieh Hsu, Sergo Jindariani, Iris Johnson, Raghav Kansal, Ryan Kastner, Erik Katsavounidis, Jeffrey D. Krupa, Pan Li, Sandeep Madireddy, Ethan Marx, Patrick McCormack, Andres Meza, Jovan Mitrevski, Mohammed Attia Mohammed, Farouk Mokhtar, Eric A. Moreno, Srishti Nagu, Rohin Narayan, Noah Palladino, Zhiqiang Que, Sang Eon Park, Subramanian Ramamoorthy, Dylan S. Rankin, Simon Rothman, Ashish Sharma, Sioni Summers, Pietro Vischia, Jean-Roch Vlimant, Olivia Weng:
Applications and Techniques for Fast Machine Learning in Science. CoRR abs/2110.13041 (2021)
2020
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Simon Reder, Jürgen Becker:
WCET-aware Code Generation and Communication Optimization for Parallelizing Compilers. DATE 2020: 210-215
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Tobias Dörr, Timo Sandmann, Jürgen Becker:
A Formal Model for the Automatic Configuration of Access Protection Units in MPSoC-Based Embedded Systems. DSD 2020: 596-603
[c354]
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Tobias Dörr, Timo Sandmann, Patrick Friederich, Arnd Leitner, Jürgen Becker:
An Approach to Cost-Efficient Fault Tolerance in Inherently Redundant Fail-Operational Systems. DSD 2020: 630-637
[c353]
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Johannes Pfau, Maximilian Reuter, Klaus Hofmann, Jürgen Becker:
Designing Universal Logic Module FPGA Architectures for Use With Ambipolar Transistor Technology. FPT 2020: 165-173
[c352]
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Victor Pazmino Betancourt, Bo Liu, Jürgen Becker:
Model-based Development of a Dynamic Container-Based Edge Computing System. ISSE 2020: 1-5
[c351]
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Matthias Kern, Emre Taspolatoglu, Fabian Scheytt, Thomas Glock, Bo Liu, Victor Pazmino Betancourt, Jürgen Becker, Eric Sax:
An Architecture-based Modeling Approach Using Data Flows for Zone Concepts in Industry 4.0. ISSE 2020: 1-8
[c350]
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Bo Liu, Victor Pazmino Betancourt, Yimeng Zhu, Jürgen Becker:
Towards an On-Demand Redundancy Concept for Autonomous Vehicle Functions using Microservice Architecture. ISSE 2020: 1-5
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Maximilian Reuter, Johannes Pfau, Tillmann A. Krauss, Mahdi Moradinasab, Udo Schwalke, Jürgen Becker, Klaus Hofmann:
Towards Ambipolar Planar Devices: The DeFET Device in Area Constrained XOR Applications. LASCAS 2020: 1-4
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Jessé Barreto de Barros, Nidhi Anantharajaiah, Mauricio Ayala-Rincón, Carlos Humberto Llanos Quintero, Jürgen Becker:
A Study of the Impact of Formulation of Cost Function in Task Mapping Problem on NoCs. NorCAS 2020: 1-7
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Simon Reder, Jürgen Becker:
Interference-Aware Memory Allocation for Real-Time Multi-Core Systems. RTAS 2020: 148-159
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Augusto W. Hoppe, Jürgen Becker, Fernanda Lima Kastensmidt:
Fine Grained Control Flow Checking with Dedicated FPGA Monitors. SoCC 2020: 219-224
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Victor Pazmino Betancourt, Thomas Glock, Aleksei Kharitonov, Matthias Kern, Bo Liu, Eric Sax, Jürgen Becker:
Linking Intrusion Detection System Information and System Model to Redesign Security Architecture. SysCon 2020: 1-7
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Tim Hotfilter, Fabian Kempf, Jürgen Becker, Dominik Reinhardt, Imen Baili:
Embedded Image Processing the European Way: A new platform for the future automotive market. WF-IoT 2020: 1-6
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Matthias Börsig, Sven Nitzsche, Max Eisele, Roland Gröll, Jürgen Becker, Ingmar Baumgart:
Fuzzing Framework for ESP32 Microcontrollers. WIFS 2020: 1-6

2010 – 2019

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2019
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Simon Reder, Fabian Kempf, Harald Bucher, Jürgen Becker, Panayiotis Alefragis, Nikolaos S. Voros, Stefanos Skalistis, Steven Derrien, Isabelle Puaut, Oliver Oey, Timo Stripf, Christian Ferdinand, Clément David, Peer Ulbig, David Müller, Umut Durak:
Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications. J. Aerosp. Inf. Syst. 16(11): 521-533 (2019)
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Shalina Percy Delicia Figuli, Jürgen Becker:
An Efficient High-Throughput Generic QAM Transmitter with Scalable Spiral FIR Filter. J. Circuits Syst. Comput. 28(1): 1950015:1-1950015:33 (2019)
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Harald Bucher, Simon Kamm, Jürgen Becker:
Cross-Layer Behavioral Modeling and Simulation of E/E-Architectures using PREEvision and Ptolemy II. Simul. Notes Eur. 29(2): 73-78 (2019)
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Maximilian Reuter, Tillmann A. Krauss, Mahdi Moradinasab, Johannes Pfau, Udo Schwalke, Jürgen Becker, Klaus Hofmann:
From MOSFETs to Ambipolar Transistors: A Static DeFET Inverter Cell for SOI. APCCAS 2019: 113-116
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Tobias Dörr, Timo Sandmann, Florian Schade, Falco K. Bapp, Jürgen Becker:
Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems. ARC 2019: 96-111
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Nadir Khan, Arthur Silitonga, Brian Pachideh, Sven Nitzsche, Jürgen Becker:
Secure Local Configuration of Intellectual Property Without a Trusted Third Party. ARC 2019: 137-146
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Leonard Masing, Fabian Lesniak, Jürgen Becker:
Hybrid Prototyping for Manycore Design and Validation. ARC 2019: 319-333
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André Bannwart Perina, Jürgen Becker, Vanderlei Bonato:
ProfCounter: Line-Level Cycle Counter for Xilinx OpenCL High-Level Synthesis. ICECS 2019: 618-621
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André Bannwart Perina, Jürgen Becker, Vanderlei Bonato:
Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSE. FPT 2019: 343-346
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Nadir Khan, Sven Nitzsche, Jürgen Becker:
A Secure Framework with Remote Configuration of Intellectual Property. ICISSP 2019: 564-571
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Nidhi Anantharajaiah, Fabian Kempf, Leonard Masing, Fabian Marc Lesniak, Jürgen Becker:
Dynamic and scalable runtime block-based multicast routing for networks on chips. NoCArc@MICRO 2019: 10:1-10:6
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Arthur Silitonga, Zhou Jiang, Nadir Khan, Jürgen Becker:
Reconfigurable Module of Multi-mode AES Cryptographic Algorithms for AP SoCs. NORCAS 2019: 1-7
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Harald Bucher, Jürgen Becker, Simon Kamm:
Cross-layer behavioral modeling and simulation of E/E-Architectures using preevision and Ptolemy II. SummerSim 2019: 18:1-18:12
[c332]
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Fabian Kempf, Nidhi Anantharajaiah, Leonard Masing, Jürgen Becker:
A Network on Chip Adapter for Real-Time and Safety-Critical Applications. SoCC 2019: 39-44
[c331]
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Florian Oszwald, Philipp Obergfell, Matthias Traub, Jürgen Becker:
Reliable Fail-Operational Automotive E/E-Architectures by Dynamic Redundancy and Reconfiguration. SoCC 2019: 203-208
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Johannes Pfau, Maximilian Reuter, Tanja Harbaum, Klaus Hofmann, Jürgen Becker:
A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s. SoCC 2019: 294-299
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Bo Liu, Victor Pazmino Betancourt, Thomas Glock, Matthias Kern, Eric Sax, Jürgen Becker:
Model-Driven Design of Tools for Multi-Domain Systems with Loosely Coupled Metamodels. SysCon 2019: 1-7
2018
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Efstathios Sotiriou-Xanthopoulos, Leonard Masing, Sotirios Xydis, Kostas Siozios, Jürgen Becker, Dimitrios Soudris:
OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures. ACM Trans. Embed. Comput. Syst. 17(5): 86:1-86:27 (2018)
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Augusto W. Hoppe, Fernanda Lima Kastensmidt, Jürgen Becker:
Control Flow Analysis for Embedded Multi-core Hybrid Systems. ARC 2018: 485-496
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Johannes Pfau, Shalina Percy Delicia Figuli, Steffen Bähr, Jürgen Becker:
Reconfigurable FPGA-Based Channelization Using Polyphase Filter Banks for Quantum Computing Systems. ARC 2018: 615-626
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Jürgen Becker, Falco K. Bapp:
The ARAMiS Project Initiative - Multicore Systems in Safety- and Mixed-Critical Applications. ARC 2018: 685-699
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Panayiotis Alefragis, George Theodoridis, Merkourios Katsimpris, Christos Valouxis, Christos Gogos, George Goulas, Nikolaos S. Voros, Simon Reder, Koray Kasnakli, Marcus Bednara, David Müller, Umut Durak, Jürgen Becker:
Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach. ARC 2018: 700-711
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Simon Reder, Leonard Masing, Harald Bucher, Timon D. ter Braak, Timo Stripf, Jürgen Becker:
A WCET-aware parallel programming model for predictability enhanced multi-core architectures. DATE 2018: 943-948
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Jürgen Becker, Viktor K. Prasanna, Markus Weimer, Wayne Luk, Kaveh Aasaraai, Derek Chiou:
RAW 2018 Invited Talks. IPDPS Workshops 2018: 81-82
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Florian Oszwald, Jürgen Becker, Philipp Obergfell, Matthias Traub:
Dynamic Reconfiguration for Real-Time Automotive Embedded Systems in Fail-Operational Context. IPDPS Workshops 2018: 206-209
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Arthur Silitonga, Florian Schade, Guanru Jiang, Jürgen Becker:
HLS-Based Performance and Resource Optimization of Cryptographic Modules. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 1009-1016
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Leonard Masing, Akshay Srivatsa, Fabian Kreß, Nidhi Anantharajaiah, Andreas Herkersdorf, Jürgen Becker:
In-NoC Circuits for Low-Latency Cache Coherence in Distributed Shared-Memory Architectures. MCSoC 2018: 138-145
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Steffen Baehr, Fabian Kempf, Jürgen Becker:
Data Readout Triggering for Phase 2 of the Belle II Particle Detector Experiment Based on Neural Networks. SoCC 2018: 174-179
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Tanja Harbaum, Matthias Norbert Balzer, Marc Weber, Jürgen Becker:
A Content - Adapted FPGA Memory Architecture with Pattern Recognition Capability and Interval Compressing Technique. SoCC 2018: 206-212
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Falco K. Bapp, Jürgen Becker:
Advances in Avionic Platforms: Multi-core Systems. Advances in Aeronautical Informatics 2018: 17-27
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Umut Durak, Jürgen Becker, Sven Hartmann, Nikolaos S. Voros:
Advances in Aeronautical Informatics, Technologies Towards Flight 4.0. Springer 2018, ISBN 978-3-319-75057-6 [contents]
2017
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Jürgen Becker:
Multicore technology in the mobility domains. it Inf. Technol. 59(5): 203-204 (2017)
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Aurang Zaib, Thomas Wild, Andreas Herkersdorf, Jan Heisswolf, Jürgen Becker, Andreas Weichslgartner, Jürgen Teich:
Efficient task spawning for shared memory and message passing in many-core architectures. J. Syst. Archit. 77: 72-82 (2017)
[j54]
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Steven Derrien, Kubilay Atasu, João M. P. Cardoso, Jürgen Becker:
Foreword to the Special Section on Reconfigurable Computing. J. Signal Process. Syst. 88(2): 103-105 (2017)
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Peter Figuli, Weiqiao Ding, Shalina Percy Delicia Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker:
Parameter Sensitivity in Virtual FPGA Architectures. ARC 2017: 141-153
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Steven Derrien, Isabelle Puaut, Panayiotis Alefragis, Marcus Bednara, Harald Bucher, Clément David, Yann Debray, Umut Durak, Imen Fassi, Christian Ferdinand, Damien Hardy, Angeliki Kritikakou, Gerard K. Rauwerda, Simon Reder, Martin Sicks, Timo Stripf, Kim Sunesen, Timon D. ter Braak, Nikolaos S. Voros, Jürgen Becker:
WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. DATE 2017: 286-289
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Dennis Weller, Fabian Oboril, Dimitar Lukarski, Jürgen Becker, Mehdi Baradaran Tahoori:
Energy Efficient Scientific Computing on FPGAs using OpenCL. FPGA 2017: 247-256
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Jürgen Becker:
Opening remarks. SoCC 2017: 1
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Jürgen Becker:
Opening remarks. SoCC 2017: 1
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Tanja Harbaum, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel, Jürgen Becker:
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration. SoCC 2017: 153-158
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Shalina Percy Delicia Figuli, Peter Figuli, Jürgen Becker:
A reconfigurable high-speed spiral FIR filter architecture. TSP 2017: 532-537
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Massimo Alioto, Hai Helen Li, Jürgen Becker, Ulf Schlichtmann, Ramalingam Sridhar:
30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017. IEEE 2017, ISBN 978-1-5386-4034-0 [contents]
2016
[j53]
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Stephan Werner, Andreas Lauber, Martijn Koedam, Jürgen Becker, Eric Sax, Kees Goossens:
Cloud-based Design and Virtual Prototyping Environment for Embedded Systems. Int. J. Online Eng. 12(9): 52-60 (2016)
[j52]
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Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker:
Providing fault tolerance through invasive computing. it Inf. Technol. 58(6): 309-328 (2016)
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Matthias Birk, Ernst Kretzek, Peter Figuli, Marc Weber, Jürgen Becker, Nicole V. Ruiter:
High-Speed Medical Imaging in 3D Ultrasound Computer Tomography. IEEE Trans. Parallel Distributed Syst. 27(2): 455-467 (2016)
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Falco K. Bapp, Oliver Sander, Timo Sandmann, Hannes Stoll, Jürgen Becker:
Programmable Logic as Device Virtualization Layer in Heterogeneous Multicore Architectures. ARC 2016: 273-286
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Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker:
A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems. ARC 2016: 343-351
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Stephanie Friederich, Niclas Lehmann, Jürgen Becker:
Adaptive Bandwidth Router for 3D Network-on-Chips. ARC 2016: 352-360
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Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker:
Adaptive Cache Structures. ARCS 2016: 87-99
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Tanja Harbaum, Mahmoud Seboui, Matthias Norbert Balzer, Jürgen Becker, Marc Weber:
A Content Adapted FPGA Memory Architecture with Pattern Recognition Capability for L1 Track Triggering in the LHC Environment. FCCM 2016: 184-191
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Stephanie Friederich, Marco Neber, Jürgen Becker:
Power Management Controller for Online Power Saving in Network-on-Chips. MCSoC 2016: 109-116
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Efstathios Sotiriou-Xanthopoulos, Leonard Masing, Kostas Siozios, George Economakos, Dimitrios Soudris, Jürgen Becker:
An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures. SAMOS 2016: 372-377
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Malgorzata Chrzanowska-Jeske, Jürgen Becker:
Tutorial 2A: 3D integration - challenges and advantages. SoCC 2016: 1-3
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Partha Pande, Jürgen Becker:
Tutorial 3A: Bringing cores closer together: The wireless revolution in on-chip communication. SoCC 2016: 1-2
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Shalina Percy Delicia Figuli, Alberto Sonnino, Peter Figuli, Jürgen Becker:
A variable FPGA based generic QAM transmitter with scalable mixed time and frequency domain signal processing. TSP 2016: 453-457
2015
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José Luis Soncco-Álvarez, Gabriel Marchesan Almeida, Jürgen Becker, Mauricio Ayala-Rincón:
Parallelization of genetic algorithms for sorting permutations by reversals over biological data. Int. J. Hybrid Intell. Syst. 12(1): 53-64 (2015)
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Simon Reder, Christoph Roth, Harald Bucher, Oliver Sander, Jürgen Becker:
Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures. Microprocess. Microsystems 39(8): 1063-1075 (2015)
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Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Stephanie Friederich, Leonard Masing, Carsten Stein, Marco Duden, Roman Klopfer, Jürgen Teich, Thomas Wild, Andreas Herkersdorf, Jürgen Becker:
Fault-tolerant communication in invasive networks on chip. AHS 2015: 1-8
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Kostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos, Shalina Percy Delicia, Dimitrios Soudris, Jürgen Becker:
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools. ARC 2015: 103-114
[c298]
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Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris, Jürgen Becker:
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware. ARC 2015: 311-320
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Aurang Zaib, Jan Heißwolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf:
Network Interface with Task Spawning Support for NoC-Based DSM Architectures. ARCS 2015: 186-198
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Stephan Werner, Bernhard Stiehle, Jürgen Becker:
Evaluation of analog and digital signal processing on PSoC architecture with DCT as use case: Comparison of an analog and software based implementation of the digital cosine transform on a Programmable System on Chip. DASIP 2015: 1-6
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Harald Bucher, Alexander Klimm, Oliver Sander, Jürgen Becker:
Power Estimation of an ECDSA Core Applied in V2X Scenarios Using Heterogeneous Distributed Simulation. DS-RT 2015: 187-194
[c294]
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Alisson Vasconcelos de Brito, Harald Bucher, Helder F. de A. Oliveira, Luis Feliphe S. Costa, Oliver Sander, Elmar U. K. Melcher, Jürgen Becker:
A Distributed Simulation Platform Using HLA for Complex Embedded Systems Design. DS-RT 2015: 195-202
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Stephan Werner, Leonard Masing, Fabian Lesniak, Jürgen Becker:
Software-in-the-Loop simulation of embedded control applications based on Virtual Platforms. FPL 2015: 1-8
[c292]
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Shalina Percy Delicia, George Ford, Peter Figuli, Jürgen Becker:
Parametric design space exploration for optimizing QAM based high-speed communication. ICCC 2015: 1-5
[c291]
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Viet Vu Duy, Oliver Sander, Timo Sandmann, Jan Heidelberger, Steffen Baehr, Jürgen Becker:
On-demand reconfiguration for coprocessors in mixed criticality multicore systems. HPCS 2015: 569-576
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Jürgen Becker, Ken Eguro, Diana Göhringer, Wayne Luk, Marco D. Santambrogio, Ramachandran Vaidyanathan, Steven J. E. Wilton:
RAW Introduction and Committees. IPDPS Workshops 2015: 68-69
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Efstathios Sotiriou-Xanthopoulos, Shalina Percy Delicia, Peter Figuli, Kostas Siozios, George Economakos, Jürgen Becker:
A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models. SAMOS 2015: 70-77
[c288]
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Benedikt Janßen, Fynn Schwiegelshohn, Martijn Koedam, François Duhem, Leonard Masing, Stephan Werner, Christophe Huriaux, Antoine Courtay, Emilie Wheatley, Kees Goossens, Fabrice Lemonnier, Philippe Millet, Jürgen Becker, Olivier Sentieys, Michael Hübner:
Designing applications for heterogeneous many-core architectures with the FlexTiles Platform. SAMOS 2015: 254-261
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Michael Dreschmann, Jan Heisswolf, Michael Geiger, Manuel Haußecker, Jürgen Becker:
A Framework for Multi-FPGA Interconnection using Multi Gigabit Transceivers. SBCCI 2015: 5:1-5:6
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Frank Hartmann, Felix Pistorius, Andreas Lauber, Kai Hildenbrand, Jürgen Becker, Wilhelm Stork:
Design of an embedded UWB hardware platform for navigation in GPS denied environments. SCVT 2015: 1-6
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Leonard Masing, Stephan Werner, Jürgen Becker:
Virtual prototyping of heterogeneous dynamic platforms using Open Virtual Platforms. SIES 2015: 152-155
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Harald Bucher, Marius-Florian Buciuman, Alexander Klimm, Oliver Sander, Jürgen Becker:
A V2X message evaluation methodology and cross-domain modelling of safety applications in V2X-enabled E/E-architectures. SimuTools 2015: 71-78
2014
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Matthias Birk, Matthias Norbert Balzer, Nicole V. Ruiter, Jürgen Becker:
Evaluation of performance and architectural efficiency of FPGAs and GPUs in the 40 and 28 nm generations for algorithms in 3D ultrasound computer tomography. Comput. Electr. Eng. 40(4): 1171-1185 (2014)
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Matthias Birk, Robin Dapp, Nicole V. Ruiter, Jürgen Becker:
GPU-based iterative transmission reconstruction in 3D ultrasound computer tomography. J. Parallel Distributed Comput. 74(1): 1730-1743 (2014)
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Matthias Birk, Michael Zapf, Matthias Norbert Balzer, Nicole V. Ruiter, Jürgen Becker:
A comprehensive comparison of GPU- and FPGA-based acceleration of reflection image reconstruction for 3D ultrasound computer tomography. J. Real Time Image Process. 9(1): 159-170 (2014)
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Carsten Tradowsky, Martin Schreiber, Malte Vesper, Ivan Domladovec, Maximilian Braun, Hans-Joachim Bungartz, Jürgen Becker:
Towards Dynamic Cache and Bandwidth Invasion. ARC 2014: 97-107
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Jürgen Becker, Thomas Bruckschlögl, Oliver Oey, Timo Stripf, George Goulas, Nick Raptis, Christos Valouxis, Panayiotis Alefragis, Nikolaos S. Voros, Christos Gogos:
Profile-Guided Compilation of Scilab Algorithms for Multiprocessor Systems. ARC 2014: 330-336
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Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Martin Karle, Maximilian Singh, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker:
The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure. ARCS Workshops 2014: 1-8
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Jan Heisswolf, Aurang Zaib, Andreas Zwinkau, Sebastian Kobbe, Andreas Weichslgartner, Jürgen Teich, Jörg Henkel, Gregor Snelting, Andreas Herkersdorf, Jürgen Becker:
CAP: Communication Aware Programming. DAC 2014: 105:1-105:6
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Lukas Meder, Philipp C. Schindler, Amos Agmon, Maxim Meltsin, Rene Bonk, Joachim Meyer, Michael Dreschmann, Alex Tolmachev, Rolf B. Hilgendorf, Moshe Nazarathy, Shalva Ben-Ezra, Thomas Pfeiffer, Wolfgang Freude, Juerg Leuthold, Christian Koos, Jürgen Becker:
Flexible real-time transmitter at 10 Gbit/s for SCFDMA PONs focusing on low-cost ONUs. DASIP 2014: 1-8
[c278]
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Oliver Sander, Timo Sandmann, Viet Vu Duy, Steffen Bähr, Falco Bapp, Jürgen Becker, Hans-Ulrich Michel, Dirk Kaule, Daniel Adam, Enno Lübbers, Jürgen Hairbucher, Andre Oliver Richter, Christian Herber, Andreas Herkersdorf:
Hardware virtualization support for shared resources in mixed-criticality multicore systems. DATE 2014: 1-6
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Christoph Roth, Simon Reder, Harald Bucher, Oliver Sander, Jürgen Becker:
Adaptive Algorithm and Tool Flow for Accelerating System C on Many-Core Architectures. DSD 2014: 137-145
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Philipp C. Schindler, Amos Agmon, Stefan Wolf, Rene Bonk, Lukas Meder, Maxim Meltsin, A. Ludwig, Jürgen Becker, Moshe Nazarathy, Shalva Ben-Ezra, Thomas Pfeiffer, Wolfgang Freude, Juerg Leuthold, Christian Koos:
Ultra-dense, single-wavelength DFT-spread OFDM PON with laserless 1 Gb/s ONU at only 300 MBd per spectral group. ECOC 2014: 1-3
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Oliver Sander, Steffen Baehr, Enno Lübbers, Timo Sandmann, Viet Vu Duy, Jürgen Becker:
A flexible interface architecture for reconfigurable coprocessors in embedded multicore systems using PCIe Single-root I/O virtualization. FPT 2014: 223-226
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Michael Dreschmann, Joachim Meyer, Philipp C. Schindler, René Schmogrow, Juerg Leuthold, Wolfgang Freude, Jürgen Becker:
An ultra-high speed OFDMA system for optical access networks. ICNC 2014: 889-894
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Jürgen Becker, Ramachandran Vaidyanathan, Marco D. Santambrogio, Jim Tørresen, Ron Sass, Philip Heng Wai Leong:
RAW Introduction and Committees. IPDPS Workshops 2014: 109-110
[c272]
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Viet Vu Duy, Timo Sandmann, Steffen Baehr, Oliver Sander, Jürgen Becker:
Virtualization Support for FPGA-Based Coprocessors Connected via PCI Express to an Intel Multicore Platform. IPDPS Workshops 2014: 305-310
[c271]
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Thomas Bruckschlögl, Oliver Oey, Michael Rückauer, Timo Stripf, Jürgen Becker:
A Hierarchical Architecture Description for Flexible Multicore System Simulation. ISPA 2014: 190-196
[c270]
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Oliver Sander, Falco Bapp, Timo Sandmann, Viet Vu Duy, Steffen Bähr, Jürgen Becker:
Architectural measures against radiation effects in multicore SoC for safety critical applications. MWSCAS 2014: 663-666
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Carsten Tradowsky, Tobias Gädeke, Thomas Bruckschlögl, Wilhelm Stork, Klaus D. Müller-Glaser, Jürgen Becker:
SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor. PDP 2014: 478-481
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Viet Vu Duy, Oliver Sander, Timo Sandmann, Steffen Bähr, Jan Heidelberger, Jürgen Becker:
Enabling partial reconfiguration for coprocessors in mixed criticality multicore systems using PCI express single-root I/O virtualization. ReConFig 2014: 1-6
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Stephanie Friederich, Jan Heisswolf, Jürgen Becker:
Hardware/software debugging of large scale many-core architectures. SBCCI 2014: 45:1-45:7
2013
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Jan Heisswolf, Ralf König, Martin Kupper, Jürgen Becker:
Providing multiple hard latency and throughput guarantees for packet switching networks on chip. Comput. Electr. Eng. 39(8): 2603-2622 (2013)
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René Cumplido, Peter Athanas, Jürgen Becker:
Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011). Int. J. Reconfigurable Comput. 2013: 597323:1-597323:2 (2013)
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Massimo Conti, Elmar U. K. Melcher, Jürgen Becker, Alisson Vasconcelos de Brito, Oliver Sander:
Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011). Int. J. Reconfigurable Comput. 2013: 942021:1-942021:2 (2013)
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Oliver Sander, Alexander Klimm, Jürgen Becker:
Hardware Support for Authentication in Cyber Physical Systems. it Inf. Technol. 55(1): 19- (2013)
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Philipp C. Schindler, René Schmogrow, Michael Dreschmann, Joachim Meyer, Ioannis Tomkos, Josep Prat, Heinz-Georg Krimmel, Thomas Pfeiffer, Pandelis Kourtessis, A. Ludwig, Djorn Karnick, David Hillerkuss, Jürgen Becker, Christian Koos, Wolfgang Freude, Juerg Leuthold:
Colorless FDMA-PON With Flexible Bandwidth Allocation and Colorless, Low-Speed ONUs [Invited]. JOCN 5(10): A204-A212 (2013)
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Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Olivier Sentieys, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, Thomas Perschke:
Compiling Scilab to high performance embedded multicore systems. Microprocess. Microsystems 37(8-C): 1033-1049 (2013)
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Diana Göhringer, Lukas Meder, Oliver Oey, Jürgen Becker:
Reliable and adaptive network-on-chip architectures for cyber physical systems. ACM Trans. Embed. Comput. Syst. 12(1s): 51:1-51:21 (2013)
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Neil W. Bergmann, Sunil Shukla, Jürgen Becker:
QUKU: A dual-layer reconfigurable architecture. ACM Trans. Embed. Comput. Syst. 12(1s): 63:1-63:26 (2013)
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Nikolaos S. Voros, Michael Hübner, Jürgen Becker, Matthias Kühnle, Florian Thoma, Arnaud Grasset, Paul Brelet, Philippe Bonnot, Fabio Campi, Eberhard Schüler, Henning Sahlbach, Sean Whitty, Rolf Ernst, Enrico Billich, Claudia Tischendorf, Ulrich Heinkel, Frank Ieromnimon, Dimitrios Kritharidis, Axel Schneider, Joachim Knäblein, Wolfram Putzke-Röming:
MORPHEUS: A heterogeneous dynamically reconfigurable platform for designing highly complex embedded systems. ACM Trans. Embed. Comput. Syst. 12(3): 70:1-70:33 (2013)
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Harry Sidiropoulos, Kostas Siozios, Peter Figuli, Dimitrios Soudris, Michael Hübner, Jürgen Becker:
JITPR: A framework for supporting fast application's implementation onto FPGAs. ACM Trans. Reconfigurable Technol. Syst. 6(2): 7:1-7:12 (2013)
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Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker:
Virtual networks - distributed communication resource management. ACM Trans. Reconfigurable Technol. Syst. 6(2): 8:1-8:14 (2013)
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Cuong Pham-Quoc, Jan Heisswolf, Stephan Werner, Zaid Al-Ars, Jürgen Becker, Koen Bertels:
Hybrid interconnect design for heterogeneous hardware accelerators. DATE 2013: 843-846
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Alexander Uhl, Jürgen Becker:
Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms. DSD 2013: 129-135
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George Goulas, Christos Valouxis, Panayiotis Alefragis, Nikolaos S. Voros, Christos Gogos, Oliver Oey, Timo Stripf, Thomas Bruckschlögl, Jürgen Becker, Ali El Moussawi, Maxime Naullet, Tomofumi Yuki:
Coarse-Grain Optimization and Code Generation for Embedded Multicore Systems. DSD 2013: 379-386
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Aurang Zaib, Jan Heisswolf, Andreas Weichslgartner, Thomas Wild, Jürgen Teich, Jürgen Becker, Andreas Herkersdorf:
AUTO-GS: Self-Optimization of NoC Traffic through Hardware Managed Virtual Connections. DSD 2013: 761-768
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Alisson Vasconcelos de Brito, Angelo V. Negreiros, Christoph Roth, Oliver Sander, Jürgen Becker:
Development and Evaluation of Distributed Simulation of Embedded Systems Using Ptolemy and HLA. DS-RT 2013: 189-196
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Harry Sidiropoulos, Peter Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker:
A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization. FPL 2013: 1-4
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Jürgen Becker, Ramachandran Vaidyanathan, Peter Athanas, Marco D. Santambrogio, René Cumplido, Oliver Sander:
RAW Introduction. IPDPS Workshops 2013: 103-105
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Jan Heisswolf, Andreas Weichslgartner, Aurang Zaib, Ralf König, Thomas Wild, Andreas Herkersdorf, Jürgen Teich, Jürgen Becker:
Hardware Supported Adaptive Data Collection for Networks on Chip. IPDPS Workshops 2013: 153-162
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Gabriel Marchesan Almeida, Oliver Bellaver Longhi, Thomas Bruckschlögl, Michael Hübner, Fabiano Hessel, Jürgen Becker:
Simplify: A Framework for Enabling Fast Functional/Behavioral Validation of Multiprocessor Architectures in the Cloud. IPDPS Workshops 2013: 2200-2205
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Peter Figuli, Carsten Tradowsky, Nadine Gaertner, Jürgen Becker:
ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores. ISSoC 2013: 1-8
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Carsten Tradowsky, Tanja Harbaum, Shaver Deyerle, Jürgen Becker:
LImbiC: An adaptable architecture description language model for developing an application-specific image processor. ISVLSI 2013: 34-39
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José Luis Soncco-Álvarez, Gabriel Marchesan Almeida, Jürgen Becker, Mauricio Ayala-Rincón:
Parallelization and virtualization of genetic algorithms for sorting permutations by reversals. NaBIC 2013: 29-35
[c254]
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Philipp C. Schindler, René Schmogrow, Michael Dreschmann, Joachim Meyer, David Hillerkuss, Ioannis Tomkos, Josep Prat, Heinz-Georg Krimmel, Thomas Pfeiffer, Pandelis Kourtessis, Jürgen Becker, Christian Koos, Wolfgang Freude, Juerg Leuthold:
Flexible WDM-PON with Nyquist-FDM and 31.25 Gbit/s per wavelength channel using colorless, low-speed ONUs. OFC/NFOEC 2013: 1-3
[c253]
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Jan Heisswolf, Maximilian Singh, Martin Kupper, Ralf König, Jürgen Becker:
Rerouting: Scalable NoC self-optimization by distributed hardware-based connection reallocation. ReConFig 2013: 1-8
[c252]
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Michael Rückauer, Daniel M. Muñoz, Timo Stripf, Oliver Oey, Carlos H. Llanos, Jürgen Becker:
A flexible implementation of the PSO algorithm for fine- and coarse-grained reconfigurable embedded systems. ReConFig 2013: 1-6
[c251]
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Michael Dreschmann, Oliver Sander, Alexander Klimm, Christoph Roth, Jürgen Becker:
Addiguration: Exploring configuration behavior of Spartan-3 devices. ReCoSoC 2013: 1-6
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Christoph Roth, Harald Bucher, Simon Reder, Oliver Sander, Jürgen Becker:
Improving parallel MPSoC simulation performance by exploiting dynamic routing delay prediction. ReCoSoC 2013: 1-8
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Ali Azarian, João M. P. Cardoso, Stephan Werner, Jürgen Becker:
An FPGA-based multi-core approach for pipelining computing stages. SAC 2013: 1533-1540
[c248]
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Jan Heisswolf, Simon Bischof, Michael Rückauer, Jürgen Becker:
Efficient memory access in 2D Mesh NoC architectures using high bandwidth routers. SBCCI 2013: 1-6
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Joachim Meyer, Michael Dreschmann, Djorn Karnick, Philipp C. Schindler, Wolfgang Freude, Juerg Leuthold, Jürgen Becker:
A novel system on chip for software-defined, high-speed OFDM signal processing. SBCCI 2013: 1-6
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Christoph Roth, Harald Bucher, Simon Reder, Florian Buciuman, Oliver Sander, Jürgen Becker:
A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation. SBCCI 2013: 1-6
2012
[j34]
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Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker:
Exploration of Uninitialized Configuration Memory Space for Intrinsic Identification of Xilinx Virtex-5 FPGA Devices. Int. J. Reconfigurable Comput. 2012: 219717:1-219717:10 (2012)
[j33]
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Diana Göhringer, Lukas Meder, Stephan Werner, Oliver Oey, Jürgen Becker, Michael Hübner:
Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration. Int. J. Reconfigurable Comput. 2012: 298561:1-298561:14 (2012)
[j32]
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Matthias Kühnle, André Wagner, Alisson Vasconcelos de Brito, Jürgen Becker:
Modeling and Implementation of a Power Estimation Methodology for SystemC. Int. J. Reconfigurable Comput. 2012: 439727:1-439727:12 (2012)
[j31]
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Christoph Roth, Joachim Meyer, Michael Rückauer, Oliver Sander, Jürgen Becker:
Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels. Int. J. Reconfigurable Comput. 2012: 729786:1-729786:13 (2012)
[j30]
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Alexander Thomas, Michael Rückauer, Jürgen Becker:
HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture. Int. J. Reconfigurable Comput. 2012: 832531:1-832531:17 (2012)
[j29]
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David Hillerkuss, René Schmogrow, Matthias Meyer, Stefan Wolf, Meinert Jordan, Philipp Kleinow, Nicole Lindenmann, Philipp C. Schindler, Argishti Melikyan, Xin Yang, Shalva Ben-Ezra, Bernd Nebendahl, Michael Dreschmann, Joachim Meyer, Francesca Parmigiani, Periklis Petropoulos, Bojan Resan, Andreas Oehler, Kurt Weingarten, Lars Altenhain, Tobias Ellermeyer, Michael Möller, Michael Hübner, Jürgen Becker, Christian Koos, Wolfgang Freude, Juerg Leuthold:
Single-Laser 325 Tbit/s Nyquist WDM Transmission. JOCN 4(10): 715-723 (2012)
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Nadine Dahm, Michael Hübner, Jürgen Becker:
FPGA system-on-chip solution for a field oriented hybrid stepper motor control. SSD 2012: 1-6
[c244]
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Michael Rückauer, Joachim Meyer, Thorsten Schubert, Michael Hübner, Dieter Scheurer, Jürgen Becker:
Realtime PCI Express monitoring for self adaptive reconfigurable systems. SSD 2012: 1-6
[c243]
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Giulio Corradi, Romuald Girardey, Jürgen Becker:
Xilinx tools facilitate development of FPGA applications for IEC61508. AHS 2012: 54-61
[c242]
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Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf König, David May:
Hardware prototyping of novel invasive multicore architectures. ASP-DAC 2012: 201-206
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Francisco Mendoza, Philipp Nenninger, Markus Ruppert, Jürgen Becker:
Scalable Problem-Oriented Approach for Dynamic Verification of Embedded Systems. CESCIT 2012: 224-229
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Max Ferger, Muhammed Al Kadi, Michael Hübner, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Gabriel Marchesan Almeida, José Rodrigo Azambuja, Jürgen Becker:
Hardware / Software Virtualization for the Reconfigurable Multicore Platform. CSE 2012: 341-344
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Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Jordy Potman, Kim Sunesen, Steven Derrien, Olivier Sentieys, Jürgen Becker:
A Compilation- and Simulation-Oriented Architecture Description Language for Multicore Systems. CSE 2012: 383-390
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Oliver Oey, Stephan Werner, Diana Göhringer, Andreas Stuckert, Jürgen Becker, Michael Hübner:
Virtualization of heterogeneous and adaptive multi-core/multi-board systems. DASIP 2012: 1-2
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Timo Stripf, Ralf König, Jürgen Becker:
A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture. DATE 2012: 21-26
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Christoph Schmutzler, Martin Simons, Jürgen Becker:
On demand dependent deactivation of automotive ECUs. DATE 2012: 69-74
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Stephan Werner, Oliver Oey, Diana Göhringer, Michael Hübner, Jürgen Becker:
Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems. DATE 2012: 280-283
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Jürgen Becker, Timo Stripf, Oliver Oey, Michael Hübner, Steven Derrien, Daniel Ménard, Olivier Sentieys, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Kostas Masselos, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Dimitrios Kritharidis, Nikolaos Mitas, Diana Göhringer:
From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach. DSD 2012: 114-121
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Michael Dreschmann, Joachim Meyer, Michael Hübner, René Schmogrow, David Hillerkuss, Jürgen Becker, Juerg Leuthold, Wolfgang Freude:
Time and frequency synchronization for ultra-high speed OFDM systems. ICNC 2012: 871-875
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Francisco Mendoza, Joris Pascal, Philipp Nenninger, Jürgen Becker:
Framework for dynamic verification of multi-domain virtual platforms in industrial automation. INDIN 2012: 935-940
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Jürgen Becker, Jinian Bian, Christophe Bobda, René Cumplido, Michael Hübner:
RAW Introduction. IPDPS Workshops 2012: 208-212
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Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker:
Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS. IPDPS Workshops 2012: 234-241
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Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker:
On Dynamic Run-time Processor Pipeline Reconfiguration. IPDPS Workshops 2012: 419-424
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Timo Stripf, Ralf König, Patrick Rieder, Jürgen Becker:
A Compiler Back-End for Reconfigurable, Mixed-ISA Processors with Clustered Register Files. IPDPS Workshops 2012: 462-469
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Jan Heisswolf, Ralf König, Jürgen Becker:
A Scalable NoC Router Design Providing QoS Support Using Weighted Round Robin Scheduling. ISPA 2012: 625-632
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Christoph Roth, Simon Reder, Gokhan Erdogan, Oliver Sander, Gabriel Marchesan Almeida, Harald Bucher, Jürgen Becker:
Asynchronous parallel MPSoC simulation on the Single-Chip Cloud Computer. ISSoC 2012: 1-8
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Matthias Birk, Matthias Norbert Balzer, Nicole V. Ruiter, Jürgen Becker:
Comparison of processing performance and architectural efficiency metrics for FPGAs and GPUs in 3D Ultrasound Computer Tomography. ReConFig 2012: 1-7
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Carsten Tradowsky, Enrique Cordero, Thorsten Deuser, Michael Hübner, Jürgen Becker:
Determination of on-chip temperature gradients on reconfigurable hardware. ReConFig 2012: 1-8
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Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, Michael Hübner, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Daniel Ménard, Olivier Sentieys, Diana Göhringer, Thomas Perschke:
A flexible approach for compiling scilab to reconfigurable multi-core embedded systems. ReCoSoC 2012: 1-8
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Fabrice Lemonnier, Philippe Millet, Gabriel Marchesan Almeida, Michael Hübner, Jürgen Becker, Sébastien Pillement, Olivier Sentieys, Martijn Koedam, Shubhendu Sinha, Kees Goossens, Christian Piguet, Marc-Nicolas Morgan, Romain Lemaire:
Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures. ICSAMOS 2012: 228-235
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Michael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg Henkel, Jürgen Becker:
Adaptive processor architecture - invited paper. ICSAMOS 2012: 244-251
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George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Christos Valouxis, Christos Gogos, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Diana Göhringer, Steven Derrien, Daniel Ménard, Olivier Sentieys, Michael Hübner, Timo Stripf, Oliver Oey, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Dimitrios Kritharidis, Nikolaos Mitas:
From Scilab to multicore embedded systems: Algorithms and methodologies. ICSAMOS 2012: 268-275
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Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker:
LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture. SIES 2012: 279-282
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Christoph Roth, Simon Reder, Oliver Sander, Michael Hübner, Jürgen Becker:
A Framework for exploration of parallel SystemC simulation on the single-chip cloud computer. SimuTools 2012: 202-207
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David Hillerkuss, René Schmogrow, Matthias Meyer, Stefan Wolf, Meinert Jordan, Philipp Kleinow, Nicole Lindenmann, Philipp C. Schindler, Argishti Melikyan, Xin Yang, Shalva Ben-Ezra, Bernd Nebendahl, Michael Dreschmann, Joachim Meyer, Francesca Parmigiani, Periklis Petropoulos, Bojan Resan, Andreas Oehler, Kurt Weingarten, Lars Altenhain, Tobias Ellermeyer, Matthias Moeller, Michael Hübner, Jürgen Becker, Christian Koos, Wolfgang Freude, Juerg Leuthold:
Single-laser 32.5 Tbit/s Nyquist WDM transmission. CoRR abs/1203.2516 (2012)
2011
[j28]
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Diana Göhringer, Michael Hübner, Etienne Nguepi Zeutebouo, Jürgen Becker:
Operating System for Runtime Reconfigurable Multiprocessor Systems. Int. J. Reconfigurable Comput. 2011: 121353:1-121353:16 (2011)
[j27]
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Aravind Dasu, João M. P. Cardoso, Eli Bozorgzadeh, Jürgen Becker:
Selected Papers from the 17th Reconfigurable Architectures Workshop (RAW2010). Int. J. Reconfigurable Comput. 2011: 574972:1-574972:2 (2011)
[j26]
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Christian Schuck, Bastian Haetzer, Jürgen Becker:
Reconfiguration Techniques for Self-X Power and Performance Management on Xilinx Virtex-II/Virtex-II-Pro FPGAs. Int. J. Reconfigurable Comput. 2011: 671546:1-671546:12 (2011)
[j25]
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Alexander Klimm, Benjamin Glas, Matthias Wachs, Sebastian Vogel, Klaus D. Müller-Glaser, Jürgen Becker:
A Security Scheme for Dependable Key Insertion in Mobile Embedded Devices. Int. J. Reconfigurable Comput. 2011: 820454:1-820454:19 (2011)
[j24]
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Benjamin Glas, Oliver Sander, Vitali Stuckert, Klaus D. Müller-Glaser, Jürgen Becker:
Prime Field ECDSA Signature Processing for Reconfigurable Embedded Systems. Int. J. Reconfigurable Comput. 2011: 836460:1-836460:12 (2011)
[j23]
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Michael Hübner, Jürgen Becker, Loïc Lagadec, Gilles Sassatelli:
Selected Papers from the International Workshop on Reconfigurable Communication-Centric Systems on Chips (ReCoSoC' 2010). Int. J. Reconfigurable Comput. 2011: 865402:1 (2011)
[j22]
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Matthias Birk, Clemens Hagner, Matthias Norbert Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker:
Evaluation of the Reconfiguration of the Data Acquisition System for 3D USCT. Int. J. Reconfigurable Comput. 2011: 952937:1-952937:9 (2011)
[j21]
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Diana Göhringer, Jonathan Obie, André L. S. Braga, Michael Hübner, Carlos H. Llanos, Jürgen Becker:
Exploration of the Power-Performance Tradeoff through Parameterization of FPGA-Based Multiprocessor Systems. Int. J. Reconfigurable Comput. 2011: 985931:1-985931:17 (2011)
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Monica Magalhães Pereira, Lars Braun, Michael Hübner, Jürgen Becker, Luigi Carro:
Run-time resource instantiation for fault tolerance in FPGAs. AHS 2011: 88-95
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Peter Figuli, Michael Hübner, Romuald Girardey, Falco Bapp, Thomas Bruckschlögl, Florian Thoma, Jörg Henkel, Jürgen Becker:
A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion. AHS 2011: 96-103
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Matthias Birk, Alexander Guth, Michael Zapf, Matthias Norbert Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker:
Acceleration of image reconstruction in 3D ultrasound computer tomography: An evaluation of CPU, GPU and FPGA computing. DASIP 2011: 67-74
[c214]
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Natalie Frietsch, I. Pashkovskiy, Gert F. Trommer, Lars Braun, Matthias Birk, Michael Hübner, Jürgen Becker:
Development of a method for image-based motion estimation of a VTOL-MAV on FPGA. DASIP 2011: 201-208
[c213]
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Joachim Meyer, Juanjo Noguera, Michael Hübner, Lars Braun, Oliver Sander, R. M. Gil, Rodney Stewart, Jürgen Becker:
Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration. DATE 2011: 1542-1547
[c212]
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Waheed Ahmed, Muhammad Shafique, Lars Bauer, Manuel Hammerich, Jörg Henkel, Jürgen Becker:
Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors. FCCM 2011: 29-32
[c211]
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Joachim Meyer, Juanjo Noguera, Michael Hübner, Rodney Stewart, Jürgen Becker:
Embedded Systems Start-Up under Timing Constraints on Modern FPGAs. FPL 2011: 103-109
[c210]
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Diana Göhringer, Stephan Werner, Michael Hübner, Jürgen Becker:
RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoC. FPL 2011: 181-184
[c209]
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Christoph Schmutzler, Andreas Krüger, Martin Simons, Jürgen Becker:
Ansätze zur Integration von energieeffizienten Intelligenten Kommunikationskontrollern für FlexRay in Autosar. GI-Jahrestagung 2011: 217
[c208]
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Jürgen Becker, Pascal Benoit, René Cumplido:
RAW Introduction. IPDPS Workshops 2011: 125-127
[c207]
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Christoph Roth, Gabriel Marchesan Almeida, Oliver Sander, Luciano Ost, Nicolas Hebert, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Jürgen Becker:
Modular Framework for Multi-level Multi-device MPSoC Simulation. IPDPS Workshops 2011: 136-142
[c206]
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Michael Hübner, Peter Figuli, Romuald Girardey, Dimitrios Soudris, Kostas Siozios, Jürgen Becker:
A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture. IPDPS Workshops 2011: 143-149
[c205]
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Ralf König, Timo Stripf, Jan Heisswolf, Jürgen Becker:
A Scalable Microarchitecture Design that Enables Dynamic Code Execution for Variable-Issue Clustered Processors. IPDPS Workshops 2011: 150-157
[c204]
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Christian Schuck, Bastian Haetzer, Michael Hübner, Jürgen Becker:
Online Routing of FPGA Clock Networks for Module Relocation in Partial Reconfigurable Multi Clock Designs. IPDPS Workshops 2011: 181-188
[c203]
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Alexander Klimm, Sebastian Vogel, Jürgen Becker:
Hyperelliptic Curve Cryptoarchitecture for Fast Execution of Schnorr and Okamoto Authentication Protocols. IPDPS Workshops 2011: 196-203
[c202]
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Matthias Rümmele-Werner, Thomas Perschke, Lars Braun, Michael Hübner, Jürgen Becker:
A FPGA based fast runtime reconfigurable real-time Multi-Object-Tracker. ISCAS 2011: 853-856
[c201]
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Alexander von Renteln, Uwe Brinkschulte, David Kramer, Wolfgang Karl, Christian Schuck, Jürgen Becker:
Digital On-demand Computing Organism - Interaction between Monitoring and Middleware. ISORC 2011: 189-196
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Christoph Schmutzler, Abdallah Lakhtel, Martin Simons, Jürgen Becker:
Increasing energy efficiency of automotive E/E-architectures with Intelligent Communication Controllers for FlexRay. SoC 2011: 92-95
[c199]
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Matthias Kühnle, Alisson Vasconcelos de Brito, Christoph Roth, Konstantinos Dagas, Jürgen Becker:
The Study of a Dynamic Reconfiguration Manager for Systems-on-Chip. ISVLSI 2011: 13-18
[c198]
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Florian Thoma, Michael Hübner, Diana Göhringer, Hasan Ümitcan Yilmaz, Jürgen Becker:
Power and performance optimization through MPI supported dynamic voltage and frequency scaling. MARC Symposium 2011: 75-78
[c197]
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Diana Göhringer, Lukas Meder, Michael Hübner, Jürgen Becker:
Adaptive Multi-client Network-on-Chip Memory. ReConFig 2011: 7-12
[c196]
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Michael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel, Jürgen Becker:
Dynamic Processor Reconfiguration. ReConFig 2011: 123-128
[c195]
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Nadine Dahm, Michael Hübner, Jürgen Becker:
Approach of an FPGA based adaptive stepper motor control system. ReCoSoC 2011: 1-6
[c194]
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Matthias Kühnle, Alisson Vasconcelos de Brito, Christoph Roth, Matthias Krüsselin, Jürgen Becker:
An approach for power and performance evaluation of reconfigurable SoC at mixed abstraction levels. ReCoSoC 2011: 1-8
[c193]
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Mahtab Niknahad, Oliver Sander, Jürgen Becker:
A study on fine granular fault tolerance methodologies for FPGAs. ReCoSoC 2011: 1-5
[c192]
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Francisco Mendoza, Christian Köllner, Jürgen Becker, Klaus D. Müller-Glaser:
An automated approach to SystemC/Simulink co-simulation. International Symposium on Rapid System Prototyping 2011: 135-141
[c191]
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Ralf König, Timo Stripf, Jan Heisswolf, Jürgen Becker:
Architecture design space exploration of run-time scalable issue-width processors. ICSAMOS 2011: 77-84
[c190]
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Timo Stripf, Ralf König, Jürgen Becker:
A novel ADL-based compiler-centric software framework for reconfigurable mixed-ISA processors. ICSAMOS 2011: 157-164
[c189]
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Diana Göhringer, Oliver Oey, Michael Hübner, Jürgen Becker:
Heterogeneous and runtime parameterizable Star-Wheels Network-on-Chip. ICSAMOS 2011: 380-387
[c188]
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Christoph Roth, Oliver Sander, Jürgen Becker:
Flexible and efficient co-simulation of networked embedded devices. SBCCI 2011: 61-66
[c187]
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Matthias Kühnle, André Wagner, Jürgen Becker:
A statistical power estimation methodology embedded in a SystemC code translator. SBCCI 2011: 79-84
[c186]
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José Rodrigo Azambuja, Samuel Pagliarini, Maurício Altieri, Fernanda Lima Kastensmidt, Michael Hübner, Jürgen Becker:
Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique. SBCCI 2011: 161-166
[c185]
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Alexander Thomas, Michael Rückauer, Jürgen Becker:
HoneyComb: an application-driven online adaptive reconfigurable hardware architecture. SBCCI 2011: 173-178
[c184]
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Christoph Roth, Oliver Sander, Matthias Kühnle, Jürgen Becker:
HLA-based simulation environment for distributed SystemC simulation. SimuTools 2011: 108-114
[c183]
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Alexander Thomas, Michael Rückauer, Jürgen Becker:
HoneyComb: A multi-grained dynamically reconfigurable runtime adaptive hardware architecture. SoCC 2011: 335-340
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Thomas Ebi, David Kramer, Christian Schuck, Alexander von Renteln, Jürgen Becker, Uwe Brinkschulte, Jörg Henkel, Wolfgang Karl:
DodOrg - A Self-adaptive Organic Many-core Architecture. Organic Computing 2011: 353-368
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Diana Göhringer, Michael Hübner, Jürgen Becker:
Adaptive Multiprocessor System-on-Chip Architecture: New Degrees of Freedom in System Design and Runtime Support. Multiprocessor System-on-Chip 2011: 127-151
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Michael Hübner, Jürgen Becker:
Multiprocessor System-on-Chip - Hardware Design and Tool Integration. Springer 2011, ISBN 978-1-4419-6459-5 [contents]
[e15]
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Diana Göhringer, Michael Hübner, Jürgen Becker:
3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, Ettlingen, Germany, July 5-6, 2011. KIT Scientific Publishing, Karlsruhe 2011, ISBN 978-3-86644-717-2 [contents]
[e14]
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Peter M. Athanas, Jürgen Becker, René Cumplido:
2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011. IEEE Computer Society 2011, ISBN 978-1-4577-1734-5 [contents]
[e13]
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Antonio Carlos Cavalcanti, Elmar U. K. Melcher, Jürgen Becker:
24th Symposium on Integrated Circuits and Systems Design, SBCCI '11, João Pessoa, Brazil, August 30 - September 2, 2011. ACM 2011, ISBN 978-1-4503-0828-1 [contents]
[e12]
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Jürgen Becker, Marcelo O. Johann, Ricardo Reis:
VLSI-SoC: Technologies for Systems Integration - 17th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2009, Florianópolis, Brazil, October 12-14, 2009, Revised Selected Papers. IFIP Advances in Information and Communication Technology 360, Springer 2011, ISBN 978-3-642-23119-3 [contents]
2010
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Roger F. Woods, Jürgen Becker, Peter Athanas, Fearghal Morgan:
Guest Editorial ARC 2009. ACM Trans. Reconfigurable Technol. Syst. 4(1): 1:1-1:2 (2010)
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Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker:
Design Assurance Strategy and Toolset for Partially Reconfigurable FPGA Systems. ACM Trans. Reconfigurable Technol. Syst. 4(1): 4:1-4:26 (2010)
[c182]
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André L. S. Braga, Carlos H. Llanos, Diana Göhringer, Jonathan Obie, Jürgen Becker, Michael Hübner:
Performance, accuracy, power consumption and resource utilization analysis for hardware / software realized Artificial Neural Networks. BIC-TA 2010: 1629-1636
[c181]
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Matthias Traub, Thilo Streichert, Oleg Krasovytskyy, Jürgen Becker:
Scenario extraction for a refined timing-analysis of automotive network topologies. DATE 2010: 81-86
[c180]
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Ralf König, Lars Bauer, Timo Stripf, Muhammad Shafique, Waheed Ahmed, Jürgen Becker, Jörg Henkel:
KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture. DATE 2010: 819-824
[c179]
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Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker:
A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip. FCCM 2010: 259-262
[c178]
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Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker:
A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only). FPGA 2010: 286
[c177]
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Michael Dreschmann, Michael Hübner, Moritz Röger, Oliver Sander, Christos Klamouris, Jürgen Becker, Wolfgang Freude, Juerg Leuthold:
Reconfigurable Hardware for Power-over-Fiber Applications. FPL 2010: 525-531
[c176]
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Jürgen Becker, Eli Bozorgzadeh, João M. P. Cardoso, Aravind Dasu:
Welcome message. IPDPS Workshops 2010: 1-2
[c175]
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Diana Göhringer, Jürgen Becker:
High performance reconfigurable multi-processor-based computing on FPGAs. IPDPS Workshops 2010: 1-4
[c174]
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Diana Göhringer, Michael Hübner, Etienne Nguepi Zeutebouo, Jürgen Becker:
CAP-OS: Operating system for runtime scheduling, task mapping and resource management on reconfigurable multiprocessor architectures. IPDPS Workshops 2010: 1-8
[c173]
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Michael Hübner, Diana Göhringer, Juanjo Noguera, Jürgen Becker:
Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs. IPDPS Workshops 2010: 1-8
[c172]
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Alexander Klimm, Matthias Haas, Oliver Sander, Jürgen Becker:
A flexible integrated cryptoprocessor for authentication protocols based on hyperelliptic curve cryptography. SoC 2010: 35-42
[c171]
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Romuald Girardey, Michael Hübner, Jürgen Becker:
Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications. ISVLSI 2010: 74-79
[c170]
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Michael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera, Rodney Stewart:
Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration. ISVLSI 2010: 190-194
[c169]
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Joachim Meyer, Michael Hübner, Lars Braun, Oliver Sander, Juanjo Noguera, Rodney Stewart, Jürgen Becker:
FPGA Startup Through Sequential Partial and Dynamic Reconfiguration. ISVLSI (Selected papers) 2010: 289-302
[c168]
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Mahtab Niknahad, Michael Hübner, Jürgen Becker:
Reliability Analysis and Improvement in Nano Scale Design. ISVLSI 2010: 299-303
[c167]
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Lars Braun, Jürgen Becker:
Two Dimensional Dynamic Multigrained Reconfigurable Hardware. ISVLSI (Selected papers) 2010: 303-318
[c166]
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Diana Göhringer, Jürgen Becker:
New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems Through Dynamic and Partial Reconfiguration: The RAMPSoC Approach. ISVLSI (Selected papers) 2010: 335-346
[c165]
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Romuald Girardey, Michael Hübner, Jürgen Becker:
Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGA. ISVLSI 2010: 469-470
[c164]
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Lars Braun, Jürgen Becker:
Two-Dimensional Dynamic Multigrained Reconfigurable Hardware. ISVLSI 2010: 475-476
[c163]
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Diana Göhringer, Jürgen Becker:
FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications. ISVLSI 2010: 477-478
[c162]
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Oliver Sander, Benjamin Glas, Lars Braun, Klaus D. Müller-Glaser, Jürgen Becker:
Intrinsic Identification of Xilinx Virtex-5 FPGA Devices Using Uninitialized Parts of Configuration Memory Space. ReConFig 2010: 13-18
[c161]
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Diana Goehringer, Jonathan Obie, Michael Hübner, Jürgen Becker:
Impact of Task Distribution, Processor Configurations and Dynamic Clock Frequency Scaling on the Power Consumption of FPGA-based Multiprocessors. ReCoSoC 2010: 13-20
[c160]
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Christian Schuck, Bastian Haetzer, Jürgen Becker:
Dynamic Online Reconfiguration of Digital Clock Managers on Xilinx Virtex-II/ Virtex II-Pro FPGAs: A Case Study of Distributed Power Management. ReCoSoC 2010: 45-50
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Florian Thoma, Jürgen Becker:
ISRC: a runtime system for heterogeneous reconfigurable architectures. ReCoSoC 2010: 59-65
[c158]
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Matthias Birk, Clemens Hagner, Matthias Norbert Balzer, Nicole V. Ruiter, Michael Hübner, Jürgen Becker:
First Evaluation of FPGA Reconfiguration for 3D Ultrasound Computer Tomography. ReCoSoC 2010: 109-114
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Benjamin Glas, Oliver Sander, Vitali Stuckert, Klaus D. Müller-Glaser, Jürgen Becker:
ECDSA Signature Processing over Prime Fields for Reconfigurable Embedded Systems. ReCoSoC 2010: 115-120
[c156]
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Alexander Klimm, Benjamin Glas, Matthias Wachs, Jürgen Becker, Klaus D. Müller-Glaser:
A Secure Keyflashing Framework for Access Systems in Highly Mobile Devices. ReCoSoC 2010: 121-126
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Diana Göhringer, Michael Hübner, Laure Hugot-Derville, Jürgen Becker:
Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC. ICSAMOS 2010: 357-364
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Alexander Thomas, Jürgen Becker:
Development and Synthesis of Adaptive Multi-grained Reconfigurable Hardware Architecture for Dynamic Function Patterns. Dynamically Reconfigurable Systems 2010: 3-24
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Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Michael Ullmann, Klaus D. Müller-Glaser, Jürgen Becker:
Adaptive Runtime System with Intelligent Allocation of Dynamically Reconfigurable Function Model and Optimized Interface Topologies. Dynamically Reconfigurable Systems 2010: 245-267
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Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede:
Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010. Dagstuhl Seminar Proceedings 10281, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany 2010 [contents]
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Viktor K. Prasanna, Jürgen Becker, René Cumplido:
ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 13-15 December 2010, Proceedings. IEEE Computer Society 2010 [contents]
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Michael Hübner, Loïc Lagadec, Oliver Sander, Jürgen Becker:
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, ReCoSoC 2010, Karlsruhe, Germany, May 17-19, 2010. KIT Scientific Reports 7551, KIT Scientific Publishing 2010, ISBN 978-3-86644-515-4 [contents]
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Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede:
10281 Abstracts Collection - Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2010
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Peter M. Athanas, Jürgen Becker, Jürgen Teich, Ingrid Verbauwhede:
10281 Summary - Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2010

2000 – 2009

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2009
[j18]
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Christian Schuck, Bastian Haetzer, Jürgen Becker:
An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing. Int. J. Reconfigurable Comput. 2009: 273791:1-273791:11 (2009)
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Diana Göhringer, Thomas Perschke, Michael Hübner, Jürgen Becker:
A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip. Int. J. Reconfigurable Comput. 2009: 395018:1-395018:11 (2009)
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Lars Braun, Diana Göhringer, Thomas Perschke, Volker Schatz, Michael Hübner, Jürgen Becker:
Adaptive real-time image processing exploiting two dimensional reconfigurable architecture. J. Real Time Image Process. 4(2): 109-125 (2009)
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Katarina Paulsson, Michael Hübner, Jürgen Becker:
Dynamic power optimization by exploiting self-reconfiguration in Xilinx Spartan 3-based systems. Microprocess. Microsystems 33(1): 46-52 (2009)
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Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner, Jürgen Becker:
FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing. ARC 2009: 62-73
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Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser:
Priority-based packet communication on a bus-shaped structure for FPGA-systems. DATE 2009: 178-183
[c152]
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Jürgen Becker:
Adaptive Multicore Systems-on-Chip (MSoC) - Design and Computing in the Nano Era. ERSA 2009: 55-66
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Diana Göhringer, Bin Liu, Michael Hübner, Jürgen Becker:
Star-Wheels Network-on-Chip featuring a self-adaptive mixed topology and a synergy of a circuit - and a packet-switching communication protocol. FPL 2009: 320-325
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Romuald Girardey, Michael Hübner, Jürgen Becker:
Dynamic reconfigurable mixed-signal architecture for safety critical applications. FPL 2009: 503-506
[c149]
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Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser:
Design of a Vehicle-to-Vehicle communication system on reconfigurable hardware. FPT 2009: 14-21
[c148]
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Alexander Klimm, Oliver Sander, Jürgen Becker:
A MicroBlaze specific co-processor for real-time hyperelliptic curve cryptography on Xilinx FPGAs. IPDPS 2009: 1-8
[c147]
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Davide Rossi, Fabio Campi, Antonio Deledda, Claudio Mucci, Stefano Pucillo, Sean Whitty, Rolf Ernst, Stéphane Chevobbe, Stéphane Guyetant, Matthias Kühnle, Michael Hübner, Jürgen Becker, Wolfram Putzke-Röming:
A multi-core signal processor for heterogeneous reconfigurable computing. SoC 2009: 106-109
[c146]
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Fabio Campi, Ralf König, Michael Dreschmann, M. Neukirchner, Damien Picard, M. Jüttner, Eberhard Schüler, Antonio Deledda, Davide Rossi, Alberto Pasini, Michael Hübner, Jürgen Becker, Roberto Guerrieri:
RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip. SoC 2009: 110-113
[c145]
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Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser:
Testing of an FPGA Based C2X-Communication Prototype with a Model Based Traffic Generation. IEEE International Workshop on Rapid System Prototyping 2009: 68-71
[c144]
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Benjamin Glas, Alexander Klimm, Klaus D. Müller-Glaser, Jürgen Becker:
Configuration Measurement for FPGA-based Trusted Platforms. IEEE International Workshop on Rapid System Prototyping 2009: 123-129
[c143]
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Oliver Sander, Christoph Roth, Vitali Stuckert, Jürgen Becker:
System concept for an FPGA based real-time capable automotive ECU simulation system. SBCCI 2009
[c142]
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Mahtab Niknahad, Michael Hübner, Jürgen Becker:
Method for improving performance in online routing of reconfigurable nano architectures. SoCC 2009: 65-68
[c141]
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Benjamin Glas, Oliver Sander, Vitali Stuckert, Klaus D. Müller-Glaser, Jürgen Becker:
Car-to-Car Communication Security on Reconfigurable Hardware. VTC Spring 2009
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Jürgen Becker, Roger F. Woods, Peter M. Athanas, Fearghal Morgan:
Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings. Lecture Notes in Computer Science 5453, Springer 2009, ISBN 978-3-642-00640-1 [contents]
2008
[j14]
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Matthias Kühnle, Michael Hübner, Jürgen Becker, Antonio Deledda, Claudio Mucci, Florian Ries, Marcello Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Tommaso DeMarco, Fabio Campi:
An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC. IEEE Des. Test Comput. 25(5): 442-451 (2008)
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Jürgen Becker, Michael Hübner, Roger F. Woods, Philip Heng Wai Leong, Robert Esser, Lionel Torres:
Current Trends on Reconfigurable Computing. Int. J. Reconfigurable Comput. 2008: 918525:1 (2008)
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Oliver Sander, Lars Braun, Michael Hübner, Jürgen Becker:
Data reallocation by exploiting FPGA configuration mechanisms. ARC 2008: 308-313
[c139]
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Alexander Klimm, Oliver Sander, Jürgen Becker, Sylvain Subileau:
A Hardware/Software Codesign of a Co-processor for Real-Time Hyperelliptic Curve Cryptography on a Spartan3 FPGA. ARCS 2008: 188-201
[c138]
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Jürgen Becker, Michael Hübner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer:
Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. DATE 2008
[c137]
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Katarina Paulsson, Michael Hübner, Jürgen Becker:
Cost-and Power Optimized FPGA based System Integration: Methodologies and Integration of a Low-Power Capacity-based Measurement Application on Xilinx FPGAs. DATE 2008: 50-55
[c136]
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Benjamin Glas, Alexander Klimm, Oliver Sander, Klaus D. Müller-Glaser, Jürgen Becker:
A System Architecture for Reconfigurable Trusted Platforms. DATE 2008: 541-544
[c135]
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Ralf König, Timo Stripf, Jürgen Becker:
A Novel Recursive Algorithm for Bit-Efficient Realization of Arbitrary Length Inverse Modified Cosine Transforms. DATE 2008: 604-609
[c134]
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Antonio Deledda, Claudio Mucci, Arseni Vitkovski, Philippe Bonnot, Arnaud Grasset, Philippe Millet, Matthias Kühnle, Florian Ries, Michael Hübner, Jürgen Becker, Massimo Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Fabio Campi, Tommaso DeMarco:
Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor. DATE 2008: 1352-1357
[c133]
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Carlos Morra, João Bispo, João M. P. Cardoso, Jürgen Becker:
Combining Rewriting-Logic, Architecture Generation, and Simulation to Exploit Coarse-Grained Reconfigurable Architectures. FCCM 2008: 320-321
[c132]
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Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker:
Fine grain reconfigurable architectures. FPL 2008: 348
[c131]
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Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
Coarse-grained reconfiguration. FPL 2008: 349
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Diana Göhringer, Michael Hübner, Thomas Perschke, Jürgen Becker:
New dimensions for multiprocessor architectures: Ondemand heterogeneity, infrastructure and performance through reconfigurability - the RAMPSoC approach. FPL 2008: 495-498
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Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker:
A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. FPL 2008: 535-538
[c128]
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Lars Braun, Katarina Paulsson, Herrmann Krömer, Michael Hübner, Jürgen Becker:
Data path driven waveform-like reconfiguration. FPL 2008: 607-610
[c127]
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Katarina Paulsson, Michael Hübner, Jürgen Becker:
Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization. FPL 2008: 699-700
[c126]
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Oliver Sander, Michael Hübner, Jürgen Becker, Matthias Traub:
Reducing latency times by accelerated routing mechanisms for an FPGA gateway in the automotive domain. FPT 2008: 97-104
[c125]
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Benjamin Glas, Alexander Klimm, Oliver Sander, Klaus D. Müller-Glaser, Jürgen Becker:
A self adaptive interfacing concept for consumer device integration into automotive entities. IPDPS 2008: 1-6
[c124]
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Diana Göhringer, Michael Hübner, Volker Schatz, Jürgen Becker:
Runtime adaptive multi-processor system-on-chip: RAMPSoC. IPDPS 2008: 1-7
[c123]
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Michael Hübner, Lars Braun, Diana Göhringer, Jürgen Becker:
Run-time reconfigurable adaptive multilayer network-on-chip for FPGA-based systems. IPDPS 2008: 1-6
[c122]
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Alexander Klimm, Lars Braun, Jürgen Becker:
An adaptive and scalable multiprocessor system For Xilinx FPGAs using minimal sized processor cores. IPDPS 2008: 1-7
[c121]
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Christian Schuck, Matthias Kühnle, Michael Hübner, Jürgen Becker:
A framework for dynamic 2D placement on FPGAs. IPDPS 2008: 1-7
[c120]
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Jürgen Becker:
Adaptive Reliable Chips - Reconfigurable Computing in the Nano Era. ISVLSI 2008: 1-2
[c119]
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Katarina Paulsson, Ulrich Viereck, Michael Hübner, Jürgen Becker:
Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs. ISVLSI 2008: 304-309
[c118]
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Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
A Web Server Based Edge Detector Implementation in FPGA. ISVLSI 2008: 441-446
[c117]
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Juanjo Noguera, Robert Esser, Katarina Paulsson, Michael Hübner, Jürgen Becker:
Towards Novel Approaches in Design Automation for FPGA Power Optimization. PATMOS 2008: 419-428
[c116]
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Benjamin Glas, Alexander Klimm, David Schwab, Klaus D. Müller-Glaser, Jürgen Becker:
A Prototype of Trusted Platform Functionality on Reconfigurable Hardware for Bitstream Updates. IEEE International Workshop on Rapid System Prototyping 2008: 135-141
[c115]
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Carlos Morra, João M. P. Cardoso, João Bispo, Jürgen Becker:
Retargeting, Evaluating, and Generating Reconfigurable Array-Based Architectures. SASP 2008: 34-41
2007
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Alexander Thomas, Jürgen Becker:
New Adaptive Multi-grained Hardware Architecture for Processing of Dynamic Function Patterns (Neue adaptive multi-granulare Hardwarearchitektur). it Inf. Technol. 49(3): 165- (2007)
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Jürgen Becker, Michael Hübner, Gerhard Hettich, Rainer Constapel, Joachim Eisenmann, Jürgen Luka:
Dynamic and Partial FPGA Exploitation. Proc. IEEE 95(2): 438-452 (2007)
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Katarina Paulsson, Michael Hübner, Günther Auer, Michael Dreschmann, Jürgen Becker:
Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs. FPL 2007: 351-356
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Christian Schuck, Stefan Lamparth, Jürgen Becker:
artNoC - A Novel Multi-Functional Router Architecture for Organic Computing. FPL 2007: 371-376
[c112]
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Florian Thoma, Matthias Kühnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen Becker:
MORPHEUS: Heterogeneous Reconfigurable Computing. FPL 2007: 409-414
[c111]
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Katarina Paulsson, Michael Hübner, Jürgen Becker, Jean-Marc Philippe, Christian Gamrat:
On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project. FPL 2007: 415-422
[c110]
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Mahendra Kumar Angamuthu Ganesan, Sundeep Singh, Frank May, Jürgen Becker:
H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture. FPL 2007: 467-471
[c109]
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Lars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach:
Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications. FPL 2007: 688-691
[c108]
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Philipp Graf, Michael Hübner, Klaus D. Müller-Glaser, Jürgen Becker:
A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures. FPL 2007: 722-725
[c107]
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Maik Boden, Thomas Fiebig, Torsten Meibner, Steffen Rülke, Jürgen Becker:
High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs. IPDPS 2007: 1-8
[c106]
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Alisson Vasconcelos de Brito, Matthias Kühnle, Elmar U. K. Melcher, Jürgen Becker:
A General Purpose Partially Reconfigurable Processor Simulator (PReProS). IPDPS 2007: 1-7
[c105]
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Carlos Morra, João M. P. Cardoso, Jürgen Becker:
Using Rewriting Logic to Match Patterns of Instructions from a Compiler Intermediate Form to Coarse-Grained Processing Elements. IPDPS 2007: 1-8
[c104]
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Thilo Pionteck, Carsten Albrecht, Roman Koch, Erik Maehle, Michael Hübner, Jürgen Becker:
Communication Architectures for Dynamically Reconfigurable FPGA Designs. IPDPS 2007: 1-8
[c103]
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Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
QUKU: A FPGA Based Flexible Coarse Grain Architecture Design Paradigm using Process Networks. IPDPS 2007: 1-7
[c102]
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Alisson Vasconcelos de Brito, Matthias Kühnle, Michael Hübner, Jürgen Becker, Elmar U. K. Melcher:
Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC. ISVLSI 2007: 35-40
[c101]
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Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele:
Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. ISVLSI 2007: 41-46
[c100]
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Katarina Paulsson, Michael Hübner, Salih Bayar, Jürgen Becker:
Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. ReCoSoC 2007: 1-6
[c99]
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Jürgen Becker, Adam Donlin, Michael Hübner:
New tool support and architectures in adaptive reconfigurable computing. VLSI-SoC 2007: 134-139
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Michael Ullmann, Wansheng Jin, Jürgen Becker:
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems. CoRR abs/0710.4850 (2007)
2006
[c98]
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Katarina Paulsson, Michael Hübner, Jürgen Becker:
Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration. AHS 2006: 288-291
[c97]
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Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection. ARC 2006: 93-98
[c96]
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Jürgen Becker, Kurt Brändle, Uwe Brinkschulte, Jörg Henkel, Wolfgang Karl, Thorsten Köster, Michael Wenz, Heinz Wörn:
Digital On-Demand Computing Organism for Real-Time Systems. ARCS Workshops 2006: 230-245
[c95]
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Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein:
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. FPL 2006: 1-4
[c94]
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Maik Boden, Steffen Rülke, Jürgen Becker:
A high-level target-precise model for designing reconfigurable HW tasks. IPDPS 2006
[c93]
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Michael Hübner, Christian Schuck, Jürgen Becker:
Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs. IPDPS 2006
[c92]
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Michael Ullmann, Jürgen Becker:
Communication concept for adaptive intelligent run-time systems supporting distributed reconfigurable embedded systems. IPDPS 2006
[c91]
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Michael Hübner, Christian Schuck, Matthias Kühnle, Jürgen Becker:
New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-time Adaptive Microelectronic Circuits. ISVLSI 2006: 97-102
[c90]
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Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
QUKU: A Two-Level Reconfigurable Architecture. ISVLSI 2006: 109-116
[c89]
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Katarina Paulsson, Michael Hübner, Markus Jung, Jürgen Becker:
Methods for Run-time Failure Recognition and Recovery in dynamic and partial Reconfigurable Systems Based on Xilinx Virtex-II Pro FPGAs. ISVLSI 2006: 159-166
[c88]
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Pascal Benoit, Lionel Torres, Gilles Sassatelli, Michel Robert, Gaston Cambon, Jürgen Becker:
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager. ISVLSI 2006: 251-256
[c87]
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Carlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein:
Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. ReCoSoC 2006: 46-51
[c86]
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Michael Hübner, Jürgen Becker:
Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration. SBCCI 2006: 1-4
[c85]
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Jürgen Becker, Michael Hübner:
Run-time reconfigurabilility and other future trends. SBCCI 2006: 9-11
[c84]
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Katarina Paulsson, Michael Hübner, Jürgen Becker:
On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. SBCCI 2006: 173-178
[e7]
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Wolfgang Karl, Jürgen Becker, Karl-Erwin Großpietsch, Christian Hochberger, Erik Maehle:
ARCS 2006 - 19th International Conference on Architecture of Computing Systems, Workshops Proceedings, March 16, 2006, Frankfurt am Main, Germany. LNI P-81, GI 2006, ISBN 3-88579-175-7 [contents]
[e6]
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Peter M. Athanas, Jürgen Becker, Gordon J. Brebner, Jürgen Teich:
Dynamically Reconfigurable Architectures, 02.04. - 07.04.2006. Dagstuhl Seminar Proceedings 06141, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany 2006 [contents]
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Claudionor José Nunes Coelho Jr., Ricardo P. Jacobi, Jürgen Becker:
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006. ACM 2006 [contents]
[i4]
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Jürgen Becker, Michael Hübner, Katarina Paulsson:
Physical 2D Morphware and Power Reduction Methods for Everyone. Dynamically Reconfigurable Architectures 2006
[i3]
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Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas:
06141 Executive Summary -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
[i2]
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Jürgen Becker, Jürgen Teich, Gordon J. Brebner, Peter M. Athanas:
06141 Abstracts Collection -- Dynamically Reconfigurable Architectures. Dynamically Reconfigurable Architectures 2006
[i1]
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Sunil Shukla, Neil W. Bergmann, Jürgen Becker:
QUKU: A Coarse Grained Paradigm for FPGAs. Dynamically Reconfigurable Architectures 2006
2005
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Jürgen Becker, Alexander Thomas:
Scalable Processor Instruction Set Extension. IEEE Des. Test Comput. 22(2): 136-148 (2005)
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Michael Ullmann, Michael Hübner, Jürgen Becker:
On-demand FPGA run-time system for flexible and dynamical reconfiguration. Int. J. Embed. Syst. 1(3/4): 193-204 (2005)
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Michael Hübner, Michael Ullmann, Jürgen Becker:
Realtime configuration code decompression for dynamic FPGA self reconfiguration: evaluation and implementation. Int. J. Embed. Syst. 1(3/4): 263-273 (2005)
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Jürgen Becker, Kurt Brändle, Michael Ullmann:
Rekonfigurierbare Hardware und intelligente Laufzeitsysteme für adaptives Rechnen. it Inf. Technol. 47(4): 201-206 (2005)
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Michael Hübner, Katarina Paulsson, Marcus Stitz, Jürgen Becker:
Novel Seamless Design-Flow for Partial and Dynamic Reconfigurable Systems with Customized Communication Structures based on Xilinx Virtex-II FPGAs. ARCS Workshops 2005: 39-44
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Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein:
FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. FPL 2005: 25-30
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Pascal Benoit, Jürgen Becker, Michel Robert, Lionel Torres, Gilles Sassatelli, Gaston Cambon:
Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors. FPL 2005: 703-706
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Michael Hübner, Katarina Paulsson, Jürgen Becker:
Parallel and Flexible Multiprocessor System-On-Chip for Adaptive Automotive Applications based on Xilinx MicroBlaze Soft-Cores. IPDPS 2005
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Michael Ullmann, Wansheng Jin, Jürgen Becker:
Hardware Enhanced Function Allocation Management in Reconfigurable Systems. IPDPS 2005
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Gerard J. M. Smit, Eberhard Schüler, Jürgen Becker, Jérôme Quévremont, Werner Brugger:
Overview of the 4S Project. SoC 2005: 70-73
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Pascal T. Wolkotte, Gerard J. M. Smit, Nikolay Kavaldjiev, Jens E. Becker, Jürgen Becker:
Energy Model of Networks-on-Chip and a Bus. SoC 2005: 82-85
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Alexander Thomas, Jürgen Becker:
Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive Reconfigurable Hardware Architectures. ISVLSI 2005: 118-123
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Carsten Bieser, Klaus D. Müller-Glaser, Jürgen Becker:
Hardware/Software Co-Training Lab: From VHDL Bit-Level Coding up to CASE-Tool Based System Modeling. MSE 2005: 51-52
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Jürgen Becker, Michael Hübner, Katarina Paulsson, Alexander Thomas:
Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. ReCoSoC 2005: 35-42
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Alexander Thomas, Jürgen Becker:
Online-adaptive Reconfigurable Hardware Architecture and Runtime Environment. SoCC 2005: 239-242
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Adam Donlin, Jürgen Becker, Michael Hübner:
I Models and Tools for the Dynamic Reconfiguration of FPGAs. SoCC 2005: 313-316
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Uwe Brinkschulte, Jürgen Becker, Dietmar Fey, Christian Hochberger, Thomas Martinetz, Christian Müller-Schloer, Hartmut Schmeck, Theo Ungerer, Rolf P. Würtz:
18th International Conference on Architecture of Computing Systems, Workshops, Innsbruck, Austria, March 2005. VDE Verlag 2005, ISBN 3-8007-2880-X [contents]
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Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic:
Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005. CSREA Press 2005, ISBN 1-932415-53-X [contents]
2004
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Jürgen Becker:
Dagstuhl-Seminar "Dynamically and Partially Reconfigurable Architectures". it Inf. Technol. 46(4): 218-225 (2004)
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Alexander Thomas, Jürgen Becker:
Aufbau- und Strukturkonzepte einer adaptive multigranularen rekonfigurierbaren Hardwarearchitektur. ARCS Workshops 2004: 165-174
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Michael Ullmann, Wansheng Jin, Jürgen Becker:
Hardware Support for QoS-based Function Allocation in Reconfigurable Systems. DATE 2004: 259-264
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Alexander Thomas, Jürgen Becker:
Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures. FPL 2004: 115-124
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Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker:
On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities. FPL 2004: 454-463
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Michael Hübner, Michael Ullmann, Lars Braun, A. Klausmann, Jürgen Becker:
Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. FPL 2004: 1037-1041
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Uwe Brinkschulte, Jürgen Becker, Klaus Dorfmüller-Ulhaas, Ralf König, Sascha Uhrig, Theo Ungerer:
CARUSO - Project Goals and Principal Approach. GI Jahrestagung (2) 2004: 616-620
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Uwe Brinkschulte, Jürgen Becker, Theo Ungerer:
CARUSO - An Approach Towards a Network of Low Power Autonomic Systems on Chips for Embedded Real-time Application. IPDPS 2004
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Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker:
An FPGA Run-Time System for Dynamical On-Demand Reconfiguration. IPDPS 2004
[c63]
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Alexander Thomas, Jürgen Becker, Ulrich Heinkel, Klaus Winkelmann, Jörg Bormann:
Formale Verifikation eines Sonet/SDH Framers. MBMV 2004: 280-288
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Michael Hübner, Tobias Becker, Jürgen Becker:
Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration. SBCCI 2004: 28-32
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Alexander Thomas, Thomas Zander, Jürgen Becker:
Adaptive DMA-based I/O interfaces for data stream handling in multi-grained reconfigurable hardware architectures. SBCCI 2004: 141-146
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Jürgen Becker, Martin Vorbach:
Coarse-grain reconfigurable XPP devices for adaptive high-end mobile video-processing. SoCC 2004: 165-166
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Uwe Brinkschulte, Jürgen Becker, Dietmar Fey, Karl-Erwin Großpietsch, Christian Hochberger, Erik Maehle, Thomas A. Runkler:
ARCS 2004 - Organic and Pervasive Computing, Workshops Proceedings, March 26, 2004, Augsburg, Germany. LNI P-41, GI 2004, ISBN 3-88579-370-9 [contents]
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Jürgen Becker, Marco Platzner, Serge Vernalde:
Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings. Lecture Notes in Computer Science 3203, Springer 2004, ISBN 3-540-22989-2 [contents]
2003
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Jürgen Becker, Reiner W. Hartenstein:
Configware and morphware going mainstream. J. Syst. Archit. 49(4-6): 127-142 (2003)
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Jürgen Becker, Alexander Thomas, Martin Vorbach, Volker Baumgarten:
An Industrial/Academic Configurable System-on-Chip Project (CSoC): Coarse-Grain XXP-/Leon-Based Architecture Integration. DATE 2003: 11120-11121
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Jürgen Becker, Martin Vorbach:
PACT XPP Architecture in Adaptive System-on-Chip Integration. Engineering of Reconfigurable Systems and Algorithms 2003: 21-30
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Martin Vorbach, Jürgen Becker:
Reconfigurable Processor Architectures for Mobile Phones. IPDPS 2003: 181
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Jürgen Becker, Martin Vorbach:
Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC). ISVLSI 2003: 107-112
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Jens E. Becker, Carsten Bieser, Alexander Thomas, Klaus D. Müller-Glaser, Jürgen Becker:
Hardware/Software Co-Training by FPGA/ASIC Synthesis and programming of a RISC Microprocessor-Core. MSE 2003: 134-135
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Jürgen Becker, Alexander Thomas, Maik Scheer:
Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. SBCCI 2003: 237-242
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Jürgen Becker, Michael Hübner, Michael Ullmann:
Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. SBCCI 2003: 283-288
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Jürgen Becker, Michael Hübner, Michael Ullmann:
Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems. VLSI-SoC (Selected Papers) 2003: 119-132
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Jürgen Becker, Michael Hübner, Michael Ullmann:
Real-Time Dynamically Run-Time Reconfiguration for Power-/Cost-optimized Virtex FPGA Realizations. VLSI-SOC 2003: 129-
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Jürgen Becker, Alexander Thomas, Maik Scheer:
Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath. VLSI-SoC (Selected Papers) 2003: 263-279
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Jürgen Becker, Alexander Thomas, Maik Scheer:
Datapath and Compiler Integration of Coarse-grain Reconfigurable XPP-Arrays into Pipelined RISC Processors. VLSI-SOC 2003: 288-
2002
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Jürgen Becker:
Configurable systems-on-chip: commercial and academic approaches. ICECS 2002: 809-812
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Chun Hok Ho, Monk-Ping Leong, Philip Heng Wai Leong, Jürgen Becker, Manfred Glesner:
Rapid Prototyping of FPGA Based Floating Point DSP Systems. IEEE International Workshop on Rapid System Prototyping 2002: 19-24
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Jürgen Becker:
Configurable Systems-on-Chip (CSoC). SBCCI 2002: 379-384
2001
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Jürgen Becker, Manfred Glesner:
A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication. J. Supercomput. 19(1): 105-127 (2001)
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Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner:
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. FPL 2001: 584-589
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Lukusa D. Kabulepa, Tideya Kella, Thilo Pionteck, Ralf Ludewig, Jürgen Becker, J. Plechinger, Manfred Glesner:
On the numerical accuracy of CORDIC-based frequency offset compensation in burst oriented OFDM systems. ICECS 2001: 1069-1072
[c43]
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Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis:
Distributed Collaborative Design over Cave2 Framework. VLSI-SOC 2001: 97-108
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Jochen Mades, Thomas Schneider, André Windisch, Thomas Hollstein, Jürgen Becker, Manfred Glesner:
Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design. MSE 2001: 2-3
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Amar Mukherjee, Nitin Motgi, Jürgen Becker, A. Friebe, C. Habermann, Manfred Glesner:
Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems. IEEE International Workshop on Rapid System Prototyping 2001: 58-63
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Jürgen Becker, Thilo Pionteck, Manfred Glesner:
Adaptive Systems-on-Chip: Architectures, Technologies and Applications. SBCCI 2001: 2-7
2000
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Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. Des. Autom. Embed. Syst. 5(3-4): 351-363 (2000)
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Frank-Michael Renner, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner:
Synthese von Kommunikationsstrukturen und architekturgenaues Rapid-Prototyping eingebetteter Echtzeitsysteme (Communication Synthesis and Architecture-Precise Rapid Prototyping of Embedded systems with Hard Real-Time Constraints). Informationstechnik Tech. Inform. 42(2): 27-33 (2000)
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Ahmad Alsolaim, Jürgen Becker, Manfred Glesner, Janusz A. Starzyk:
A dynamically reconfigurable system-on-a-chip architecture for future mobile digital signal processing. EUSIPCO 2000: 1-4
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Ahmad Alsolaim, Janusz A. Starzyk, Jürgen Becker, Manfred Glesner:
Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems. FCCM 2000: 205-216
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Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
Field Programmable Communication Emulation and Optimization for Embedded System Design. FPL 2000: 58-67
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Jürgen Becker, Thilo Pionteck, Manfred Glesner:
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. FPL 2000: 312-321
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Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
Communication Performance Estimation and Communication Synthesis for Architecture-precise Prototyping of Real-time Embedded Systems. MBMV 2000: 227-235
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Jürgen Becker, Manfred Glesner:
IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures. PDPTA 2000
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Jürgen Becker, Manfred Glesner, Ahmad Alsolaim, Janusz A. Starzyk:
Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures. PDPTA 2000
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Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems. IEEE International Workshop on Rapid System Prototyping 2000: 154-159
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Jürgen Becker, Lukusa D. Kabulepa, Frank-Michael Renner, Manfred Glesner:
Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications. IEEE International Workshop on Rapid System Prototyping 2000: 160-
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Jürgen Becker, Thilo Pionteck, Manfred Glesner:
An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing. SBCCI 2000: 341-346

1990 – 1999

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1999
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Marc Theisen, Jürgen Becker, Manfred Glesner, Tri Caohuu:
Parallel Hardware Compilation in Complex Hardware/Software Systems based on High-Level Code Transformations. ARCS 1999: 143-154
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Tri Caohuu, Thuy Trong Le, Manfred Glesner, Jürgen Becker:
Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching. FPL 1999: 507-513
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Andreas Kirschbaum, Jürgen Becker, Manfred Glesner:
ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect. VLSI 1999: 659-670
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Matthias Meixner, Jürgen Becker, Thomas Hollstein, Manfred Glesner:
Object-oriented Specification Approach for Synthesis of Hardware-/Software Systems. MBMV 1999: 182-191
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Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. IEEE International Workshop on Rapid System Prototyping 1999: 108-113
1998
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Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger:
Parallelization in Co-Compilation for Configurable Accelerators. ASP-DAC 1998: 23-33
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Thomas Hollstein, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner:
HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. CODES 1998: 29-33
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Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner:
Perspectives of Reconfigurable Computing in Research, Industry and Education. FPL 1998: 39-48
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Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications. FPL 1998: 179-188
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Jürgen Becker, Karin Schmidt:
Automatic Parallelism Exploitation for FPL-Based Accelerators. HICSS (7) 1998: 169-178
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Andreas Kirschbaum, Jürgen Becker, Manfred Glesner:
A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems. IPPS/SPDP Workshops 1998: 61-66
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Jürgen Becker, Reiner W. Hartenstein:
Real-Time Prototyping in Microprocessor/Accelerator Symbiosis. International Workshop on Rapid System Prototyping 1998: 32-38
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Andreas Kirschbaum, Jürgen Becker, Manfred Glesner:
Run-Time Monitoring of Communication Activities in a Rapid Prototyping Environment. International Workshop on Rapid System Prototyping 1998: 52-57
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Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner:
Internet-based Training of Reconfigurable Technologies. SBCCI 1998: 25-30
1997
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Jürgen Becker:
A partitioning compiler for computers with Xputer-based accelerators. Kaiserslautern University of Technology, Germany, 1997, pp. I-X, 1-309
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Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
A Novel Universal Sequencer Hardware. ARCS 1997: 143-152
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Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
A Novel Sequencer Hardware for Application Specific Computing. ASAP 1997: 392-401
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Reiner W. Hartenstein, Jürgen Becker:
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. CODES 1997: 141-145
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Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
Data scheduling to increase performance of parallel accelerators. FPL 1997: 294-303
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Reiner W. Hartenstein, Jürgen Becker:
A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. HICSS (5) 1997: 125-134
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Reiner W. Hartenstein, Jürgen Becker:
Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. VLSI Design 1997: 146-150
1996
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Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig:
High-performance computing using a reconfigurable accelerator. Concurr. Pract. Exp. 8(6): 429-443 (1996)
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Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger:
A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP 1996: 274-283
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Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. CODES 1996: 77-84
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Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
Two-Level Hardware/Software Partitioning Using CoDe-X. ECBS 1996: 395-
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Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
An Embedded Accelerator for Real-Time Image Processing. RTS 1996: 83-88
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Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. FPL 1996: 65-76
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Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger:
A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS 1996: 544-548
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Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig:
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design 1996: 81-84
1995
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Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt:
A Parallelizing Compilation Method for the Map-oriented Machine. ASAP 1995: 129-132
1994
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Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt:
Data-Procedural Languages for FPL-based Machines. FPL 1994: 183-195

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