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2020 – today
- 2024
[c32]Reoma Matsuo, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya:
Branch Divergence-Aware Flexible Approximating Technique on GPUs. COOL CHIPS 2024: 1-6- [c31]Masayuki Kimura
, Ryota Shioya:
ReOVE: Restricted Out-of-Order Execution for Superscalar Processors with Vector Extension. ISLPED 2024: 1-6 - [c30]Soramichi Akiyama, Ryota Shioya, Yuto Miyatake, Tongxin Yang:
Error Distribution Estimation for Fixed-point Arithmetic using Program Derivatives. ISQED 2024: 1-9 - [c29]Eri Ogawa, Tetsuro Yamazaki, Ryota Shioya:
Dynamic Possible Source Count Analysis for Data Leakage Prevention. MPLR 2024: 98-111 - 2023
- [j16]Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
A Principal Factor of Performance in Decoupled Front-End. IEICE Trans. Inf. Syst. 106(12): 1960-1968 (2023) - [j15]Tetsuro Yamazaki, Tomoki Nakamaru, Ryota Shioya, Tomoharu Ugawa, Shigeru Chiba:
Collecting Cyclic Garbage across Foreign Function Interfaces: Who Takes the Last Piece of Cake? Proc. ACM Program. Lang. 7(PLDI): 591-614 (2023) - [c28]Chenlin Shi, Shinobu Miwa, Tongxin Yang, Ryota Shioya, Hayato Yamaki, Hiroki Honda:
CNFET7: An Open Source Cell Library for 7-nm CNFET Technology. ASP-DAC 2023: 763-768 - [c27]Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
A Sound and Complete Algorithm for Code Generation in Distance-Based ISA. CC 2023: 73-84 - [c26]Yi Ge, Katsuhiro Yoda, Makiko Ito, Toshiyuki Ichiba, Takahide Yoshikawa, Ryota Shioya, Masahiro Goshima:
Out-of-Step Pipeline for Gather/Scatter Instructions. DATE 2023: 1-2 - [c25]Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya:
TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA. DATE 2023: 1-2 - [c24]Yuichi Sugiyama, Reoma Matsuo, Ryota Shioya:
SurgeFuzz: Surge-Aware Directed Fuzzing for CPU Designs. ICCAD 2023: 1-9 - [c23]Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS. ISCAS 2023: 1-5 - [c22]Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors. MICRO 2023: 1-16 - [i2]Naoya Hatta, Shuntaro Tsunoda, Kouhei Uchida, Taichi Ishitani, Ryota Shioya, Kei Ishii:
PEZY-SC3: A MIMD Many-core Processor for Energy-efficient Computing. CoRR abs/2301.07510 (2023) - 2022
- [j14]Yasutaka Matsuda, Ryota Shioya, Hideki Ando:
Reducing Energy Consumption of Wakeup Logic through Double-Stage Tag Comparison. IEICE Trans. Inf. Syst. 105-D(2): 320-332 (2022) - [c21]Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya:
T-SKID: Predicting When to Prefetch Separately from Address Prediction. DATE 2022: 1389-1394 - 2021
- [c20]Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. ICCD 2021: 88-92 - [c19]Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai:
Compiling and Optimizing Real-world Programs for STRAIGHT ISA. ICCD 2021: 400-408 - [c18]Soramichi Akiyama, Ryota Shioya:
The Granularity Gap Problem: A Hurdle for Applying Approximate Memory to Complex Data Layout. ICPE 2021: 125-132 - [i1]Soramichi Akiyama, Ryota Shioya:
The Granularity Gap Problem: A Hurdle for Applying Approximate Memory to Complex Data Layout. CoRR abs/2101.10605 (2021) - 2020
- [c17]Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
A High-Performance Out-of-Order Soft Processor Without Register Renaming. FPL 2020: 73-78 - [c16]Susumu Mashimo, Ryota Shioya, Koji Inoue:
Energy Efficient Runahead Execution on a Tightly Coupled Heterogeneous Core. HPC Asia 2020: 207-216
2010 – 2019
- 2019
- [j13]Reoma Matsuo, Ryota Shioya, Hideki Ando:
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline. IEEE Comput. Archit. Lett. 18(2): 170-173 (2019) - [c15]Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima:
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. FPT 2019: 63-71 - 2018
- [j12]Susumu Mashimo, Ryota Shioya, Koji Inoue:
VMOR: Microarchitectural Support for Operand Access in an Interpreter. IEEE Comput. Archit. Lett. 17(2): 217-220 (2018) - [j11]Keita Doi, Ryota Shioya, Hideki Ando:
Performance Improvement Techniques in Tightly Coupled Multicore Architectures for Single-Thread Applications. J. Inf. Process. 26: 445-460 (2018) - [j10]Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
Bank-Aware Instruction Scheduler for a Multibanked Register File. J. Inf. Process. 26: 696-705 (2018) - [c14]Yasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando:
A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power Mode. ARCS 2018: 211-224 - [c13]Junichiro Kadomoto, Toru Koizumi, Akifumi Fukuda, Reoma Matsuo, Susumu Mashimo, Akifumi Fujita, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai:
An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming. FPT 2018: 374-377 - [c12]Ushio Jimbo, Ryota Shioya, Masahiro Goshima:
Application of Timing Fault Detection to Rocket Core on FPGA. CANDAR Workshops 2018: 178-181 - [c11]Shinji Sakai, Taishi Suenaga, Ryota Shioya, Hideki Ando:
Rearranging Random Issue Queue with High IPC and Short Delay. ICCD 2018: 123-131 - [c10]Tomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura:
Isolation-Safe Speculative Access Control for Hardware Transactional Memory. ICECS 2018: 517-520 - [c9]Yuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura:
An Analysis and a Solution of False Conflicts for Hardware Transactional Memory. ICECS 2018: 529-532 - [c8]Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai:
STRAIGHT: Hazardless Processor Architecture Without Register Renaming. MICRO 2018: 121-133 - 2017
- [j9]Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. IEICE Trans. Electron. 100-C(3): 232-244 (2017) - [j8]Ushio Jimbo, Junji Yamada, Ryota Shioya, Masahiro Goshima:
Applying Razor Flip-Flops to SRAM Read Circuits. IEICE Trans. Electron. 100-C(3): 245-258 (2017) - [j7]Junji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
Skewed Multistaged Multibanked Register File for Area and Energy Efficiency. IEICE Trans. Inf. Syst. 100-D(4): 822-837 (2017) - [c7]Tomoki Tajimi, Anju Hirota, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura:
Initial study of a phase-aware scheduling for hardware transactional memory. PACRIM 2017: 1-6 - 2016
- [j6]Hideki Ando, Ryota Shioya:
Performance of Dynamic Instruction Window Resizing for a Given Power Budget under DVFS Control. IEICE Trans. Inf. Syst. 99-D(2): 341-350 (2016) - [j5]Ryota Shioya, Hideki Ando:
Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency. IEICE Trans. Inf. Syst. 99-D(3): 630-640 (2016) - [j4]Ryota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando:
FXA: Executing Instructions in Front-End for Energy Efficiency. IEICE Trans. Inf. Syst. 99-D(4): 1092-1107 (2016) - 2015
- [j3]Naruki Kurata, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
Address Order Violation Detection with Parallel Counting Bloom Filters. IEICE Trans. Electron. 98-C(7): 580-593 (2015) - 2014
- [c6]Ryota Shioya, Hideki Ando:
Energy efficiency improvement of renamed trace cache through the reduction of dependent path length. ICCD 2014: 416-423 - [c5]Ryota Shioya, Masahiro Goshima, Hideki Ando:
A Front-End Execution Architecture for High Energy Efficiency. MICRO 2014: 419-431 - 2013
- [j2]Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, Shuichi Sakai:
Register Indirect Jump Target Forwarding. IEICE Trans. Inf. Syst. 96-D(2): 278-288 (2013) - 2011
- [j1]Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai:
Low-Overhead Architecture for Security Tag. IEICE Trans. Inf. Syst. 94-D(1): 69-78 (2011) - 2010
- [c4]Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai:
Register Cache System Not for Latency Reduction Purpose. MICRO 2010: 301-312
2000 – 2009
- 2009
- [c3]Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai:
Low-Overhead Architecture for Security Tag. PRDC 2009: 135-142 - [c2]Kunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai:
String-Wise Information Flow Tracking against Script Injection Attacks. PRDC 2009: 169-176 - 2006
- [c1]Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai:
Base Address Recognition with Data Flow Tracking for Injection Attack Detection. PRDC 2006: 165-172
Coauthor Index
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last updated on 2024-10-23 20:23 CEST by the dblp team
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