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2020 – today
- 2022
[j2]Jihyo Kang
, Jaehyeok Yang, Kyunghoon Kim, Joo-Hyung Chae, Gang-Sik Lee, Sang-Yeon Byeon, Boram Kim, Dong-Hyun Kim, Youngtaek Kim, Yeongmuk Cho, Junghwan Ji, Sera Jeong, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Sunho Kim, Hae-Kang Jung, Jieun Jang, Sangkwon Lee, Hyungsoo Kim, Joo-Hwan Cho, Junhyun Chun, Seon-Yong Cha:
A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. IEEE J. Solid State Circuits 57(1): 212-223 (2022)- 2021
- [c1]Kyunghoon Kim, Joo-Hyung Chae, Jaehyeok Yang, Jihyo Kang, Gang-Sik Lee, Sang-Yeon Byeon, Youngtaek Kim, Boram Kim, Dong-Hyun Kim, Yeongmuk Cho, Kangmoo Choi, Hyeongyeol Park, Junghwan Ji, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Minsoo Park, Hongdeuk Kim, Sijun Park, Kyubong Kong, Sunho Kim, Sangkwon Lee, Junhyun Chun, Hyungsoo Kim, Seon-Yong Cha:
A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation. ISSCC 2021: 344-346
2010 – 2019
- 2012
- [j1]In-Young Chung, Seong Yeol Jeong, Sung Min Seo, Myungjin Lee, Taesu Jang, Seon-Yong Cha, Young June Park:
New Multiple-Times Programmable CMOS ROM Cell. IEICE Trans. Electron. 95-C(6): 1098-1103 (2012)
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