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ORCIDJosé Flich
José Flich Cardo
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- affiliation: Technical University of Valencia, Department of Computer Architecture, Spain
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2020 – today
- 2023
[c129]Xabier Iturbe, Nassim Abderrahmane, Jaume Abella
, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov:
NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. DATE 2023: 1-6- [c128]David Rodriguez, Rafael Tornero, José Flich:
Towards Efficient Neural Network Model Parallelism on Multi-FPGA Platforms. DATE 2023: 1-6 - [c127]Rafael Tornero, David Rodriguez, José Maria Martínez, José Flich:
An Open-Source FPGA Platform for Shared-Memory Heterogeneous Many-Core Architecture Exploration. DCIS 2023: 1-6 - [c126]Jie Lei, José Flich, Enrique S. Quintana-Ortí:
Toward Matrix Multiplication for Deep Learning Inference on the Xilinx Versal. PDP 2023: 227-234 - [c125]Jie Lei, Héctor Martínez, José Flich, Enrique S. Quintana-Ortí:
GEMM-Like Convolution for Deep Learning Inference on the Xilinx Versal. ISC Workshops 2023: 593-604 - [i6]Jie Lei, José Flich, Enrique S. Quintana-Ortí:
Toward matrix multiplication for deep learning inference on the Xilinx Versal. CoRR abs/2302.07594 (2023) - 2022
- [j51]Jorge Ejarque, Rosa M. Badia, Loïc Albertin, Giovanni Aloisio, Enrico Baglione, Yolanda Becerra, Stefan Boschert, Julian R. Berlin, Alessandro D'Anca, Donatello Elia, François Exertier, Sandro Fiore, José Flich, Arnau Folch, Steven J. Gibbons, Nikolay Koldunov, Francesc Lordan, Stefano Lorito, Finn Løvholt, Jorge Macías Sánchez, Fabrizio Marozzo, Alberto Michelini, Marisol Monterrubio Velasco, Marta Pienkowska, Josep de la Puente, Anna Queralt, Enrique S. Quintana-Ortí, Juan Esteban Rodriguez, Fabrizio Romano, Riccardo Rossi, Jedrzej Rybicki, Miroslaw Kupczyk, Jacopo Selva, Domenico Talia, Roberto Tonini, Paolo Trunfio, Manuela Volpe:
Enabling dynamic and intelligent workflows for HPC, data analytics, and AI convergence. Future Gener. Comput. Syst. 134: 414-429 (2022) - [c124]Laura Medina, Salva Carrion, Pablo Andreu, Tomás Picornell, José Flich, Carles Hernández, Michael Sandoval, Markel Sainz, Charles-Alexis Lefebvre, Martin Rönnbäck, Martin Matschnig, Matthias Wess, Herbert Taucher:
The SELENE Deep Learning Acceleration Framework for Safety-related Applications. DATE 2022: 636-639 - [c123]José Flich, Laura Medina, Izan Catalán, Carles Hernández, Andrea Bragagnolo, Fabrice Auzanneau, David Briand:
Efficient Inference Of Image-Based Neural Network Models In Reconfigurable Systems With Pruning And Quantization. ICIP 2022: 2491-2495 - [p1]Marco Aldinucci, David Atienza, Federico Bolelli, Mónica Caballero, Iacopo Colonnelli, José Flich, Jon Ander Gómez, David González, Costantino Grana, Marco Grangetto, Simone Leo, Pedro López, Dana Oniga, Roberto Paredes, Luca Pireddu, Eduardo Quiñones, Tatiana Silva, Enzo Tartaglione, Marina Zapater:
The DeepHealth Toolkit: A Key European Free and Open-Source Software for Deep Learning and Computer Vision Ready to Exploit Heterogeneous HPC and Cloud Architectures. Technologies and Applications for Big Data Value 2022: 183-202 - [i5]Jorge Ejarque, Rosa M. Badia, Loïc Albertin, Giovanni Aloisio, Enrico Baglione, Yolanda Becerra, Stefan Boschert, Julian R. Berlin, Alessandro D'Anca, Donatello Elia, François Exertier, Sandro Fiore, José Flich, Arnau Folch, Steven J. Gibbons, Nikolay Koldunov, Francesc Lordan, Stefano Lorito, Finn Løvholt, Jorge Macías Sánchez, Fabrizio Marozzo, Alberto Michelini, Marisol Monterrubio Velasco, Marta Pienkowska, Josep de la Puente, Anna Queralt, Enrique S. Quintana-Ortí, Juan Esteban Rodriguez, Fabrizio Romano, Riccardo Rossi, Jedrzej Rybicki, Miroslaw Kupczyk, Jacopo Selva, Domenico Talia, Roberto Tonini, Paolo Trunfio, Manuela Volpe:
Enabling Dynamic and Intelligent Workflows for HPC, Data Analytics, and AI Convergence. CoRR abs/2204.09287 (2022) - 2021
- [j50]Tomás Picornell, José Flich, Carles Hernández, José Duato:
Enforcing Predictability of Many-Cores With DCFNoC. IEEE Trans. Computers 70(2): 270-283 (2021) - [j49]Juan-José Crespo, José L. Sánchez, Francisco J. Alfaro-Cortés, José Flich, José Duato:
UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibility. J. Supercomput. 77(11): 12826-12856 (2021) - [c122]José Flich, Rafael Tornero, David Rodriguez, Davide Russo, José Maria Martínez, Carles Hernández:
From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience. DATE 2021: 7-12 - [c121]Ilya Tuzov, Pablo Andreu, Laura Medina, Tomás Picornell, Antonio Robles, Pedro López, José Flich, Carles Hernández:
Improving the Robustness of Redundant Execution with Register File Randomization. ICCAD 2021: 1-9 - [e4]João Bispo, Stefano Cherubin, José Flich:
12th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and 10th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, PARMA-DITAM 2021, January 19, 2021, Budapest, Hungary. OASIcs 88, Schloss Dagstuhl - Leibniz-Zentrum für Informatik 2021, ISBN 978-3-95977-181-8 [contents] - [i4]Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich Cardo, Carles Hernández Luz, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater:
The RECIPE Approach to Challenges in Deeply Heterogeneous High Performance Systems. CoRR abs/2103.03044 (2021) - 2020
- [j48]Tomás Picornell, José Flich, José Duato, Carles Hernández:
HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory. IEEE Access 8: 194836-194849 (2020) - [j47]Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich Cardo, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater:
The RECIPE approach to challenges in deeply heterogeneous high performance systems. Microprocess. Microsystems 77: 103185 (2020) - [c120]Carles Hernández, José Flich, Roberto Paredes, Charles-Alexis Lefebvre, Imanol Allende, Jaume Abella, David Trillin, Martin Matschnig, Bernhard Fischer, Konrad Schwarz, Jan Kiszka, Martin Rönnbäck, Johan Klockars, Nicholas Mc Guire, Franz Rammerstorfer, Christian Schwarzl, Franck Wartel, Dierk Lüdemann, Mikel Labayen:
SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems. DSD 2020: 370-377 - [c119]José Flich, Carles Hernández, Eduardo Quiñones, Roberto Paredes:
Distributed Training on a Highly Heterogeneous HPC System. SAMOS 2020: 359-370 - [i3]Juan-José Crespo, José L. Sánchez, Francisco J. Alfaro-Cortes, José Flich, José Duato:
UPR: Deadlock-Free Dynamic Network Reconfiguration by Exploiting Channel Dependency Graph Compatibility. CoRR abs/2006.02332 (2020) - [i2]Juan-José Crespo, German Maglione Mathey, José L. Sánchez, Francisco J. Alfaro-Cortes, José Flich:
TDSR: Transparent Distributed Segment-Based Routing. CoRR abs/2006.04549 (2020)
2010 – 2019
- 2019
- [j46]Edoardo Fusella, Mahdi Nikdast, Ian O'Connor, José Flich, Sudeep Pasricha:
Guest Editors' Introduction: Emerging Networks-on-Chip Designs, Technologies, and Applications. ACM J. Emerg. Technol. Comput. Syst. 15(1): 1:1-1:2 (2019) - [c118]Tomás Picornell, José Flich, Carles Hernández, José Duato:
DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip. DAC 2019: 95 - [c117]Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater:
Challenges in Deeply Heterogeneous High Performance Systems. DSD 2019: 428-435 - [c116]Miguel Gorgues Alonso, José Flich, Meriem Turki, Davide Bertozzi:
A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems. MCSoC 2019: 149-156 - 2018
- [j45]José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni:
Exploring manycore architectures for next-generation HPC systems through the MANGO approach. Microprocess. Microsystems 61: 154-170 (2018) - [j44]Miguel Gorgues Alonso, José Flich:
PROSA: Protocol-Driven Network on Chip Architecture. IEEE Trans. Parallel Distributed Syst. 29(7): 1560-1574 (2018) - [c115]William Fornaciari, Giovanni Agosta, David Atienza, Carlo Brandolese, Leila Cammoun, Luca Cremona, Alessandro Cilardo, Albert Farrés, José Flich, Carles Hernández, Michal Kulchewski, Simone Libutti, José Maria Martínez, Giuseppe Massari, Ariel Oleksiak, Anna Pupykina, Federico Reghenzani, Rafael Tornero, Michele Zanella, Marina Zapater, Davide Zoni:
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. SAMOS 2018: 187-194 - 2017
- [j43]Edoardo Fusella, José Flich, Alessandro Cilardo:
Path Setup for Hybrid NoC Architectures Exploiting Flooding and Standby. IEEE Trans. Parallel Distributed Syst. 28(5): 1403-1416 (2017) - [c114]José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Gerald Guillaume, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Simone Libutti, Bruno Maitre, José Maria Martínez, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Tomás Picornell, Igor Piljic, Anna Pupykina, Federico Reghenzani, Isabelle Staub, Rafael Tornero, Marina Zapater, Davide Zoni:
MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. DSD 2017: 478-485 - [c113]José V. Escamilla, José Flich, Mario R. Casu:
ICARO-PAPM: Congestion Management with Selective Queue Power-Gating. HPCS 2017: 259-266 - [c112]José Flich, Alessandro Cilardo, Mario Kovaç, Rafael Tornero, Mirko Gagliardi, Edoardo Fusella, José Maria Martínez, Tomás Picornell:
Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration. PARCO 2017: 381-389 - 2016
- [j42]Miguel Gorgues, José Flich:
End-Point Congestion Filter for Adaptive Routing with Congestion-Insensitive Performance. IEEE Comput. Archit. Lett. 15(1): 9-12 (2016) - [j41]Davide Zoni, José Flich, William Fornaciari:
CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs. IEEE Trans. Parallel Distributed Syst. 27(6): 1603-1616 (2016) - [c111]José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni:
Enabling HPC for QoS-sensitive applications: The MANGO approach. DATE 2016: 702-707 - [c110]José V. Escamilla, Mario R. Casu, José Flich:
Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management Strategy. MCSoC 2016: 241-248 - [c109]Miguel Gorgues Alonso, José Flich Cardo:
PROSA: protocol-driven NoC architecture. NOCS 2016: 1-8 - [c108]Behrad Niazmand, Siavoosh Payandeh Azad, José Flich, Jaan Raik, Gert Jervan, Thomas Hollstein:
Logic-based implementation of fault-tolerant routing in 3D network-on-chips. NOCS 2016: 1-8 - 2015
- [j40]Antoni Roca, Carles Hernández, Mario Lodde, José Flich:
Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems. Comput. Electr. Eng. 45: 374-385 (2015) - [j39]Davide Bertozzi, Giorgos Dimitrakopoulos, José Flich, Sören Sonntag:
The fast evolving landscape of on-chip communication - Selected future challenges and research avenues. Des. Autom. Embed. Syst. 19(1-2): 59-76 (2015) - [j38]Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, José Flich, Francisco Triviño:
A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs" [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106]. ACM Trans. Embed. Comput. Syst. 14(1): 2:1-2:9 (2015) - [j37]Jesús Escudero-Sahuquillo, Ernst Gunnar Gran, Pedro Javier García, José Flich, Tor Skeie, Olav Lysne, Francisco J. Quiles, José Duato:
Efficient and Cost-Effective Hybrid Congestion Control for HPC Interconnection Networks. IEEE Trans. Parallel Distributed Syst. 26(1): 107-119 (2015) - [c107]José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Alessandro Cilardo, William Fornaciari, Mario Kovac, Fabrice Roudet, Davide Zoni:
The MANGO FET-HPC Project: An Overview. CSE 2015: 351-354 - [c106]Rimpy Bishnoi, Vijay Laxmi, Manoj Singh Gaur, José Flich:
d2-LBDR: distance-driven routing to handle permanent failures in 2D mesh NOCs. DATE 2015: 800-805 - [c105]Marco Balboni, José Flich, Davide Bertozzi:
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration. DATE 2015: 806-811 - [c104]José V. Escamilla, José Flich, Pedro Javier García:
Efficient DVFS Operation in NoCs Through a Proper Congestion Management Strategy. Euro-Par Workshops 2015: 339-351 - [c103]Edoardo Fusella, José Flich, Alessandro Cilardo, Antonino Mazzeo:
On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs. SiPhotonics@HiPEAC 2015: 9-16 - [c102]Alessandro Cilardo, José Flich, Mirko Gagliardi, Rafael Tornero Gavilá:
Customizable Heterogeneous Acceleration for Tomorrow's High-Performance Computing. HPCC/CSS/ICESS 2015: 1181-1185 - [e3]André Ivanov, Diana Marculescu, Partha Pratim Pande, José Flich, Karthik Pattabiraman:
Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015. ACM 2015, ISBN 978-1-4503-3396-2 [contents] - 2014
- [j36]Mario Lodde, José Flich:
Runtime home mapping for effective memory resource usage. Microprocess. Microsystems 38(4): 276-291 (2014) - [j35]José Cano, José Flich, Antoni Roca, José Duato, Marcello Coppola, Riccardo Locatelli:
Efficient Routing in Heterogeneous SoC Designs with Small Implementation Overhead. IEEE Trans. Computers 63(3): 557-569 (2014) - [j34]Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, José Flich, Hannu Tenhunen:
Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing. IEEE Trans. Computers 63(3): 718-733 (2014) - [c101]Miguel Gorgues, Dong Xiang, José Flich, Zhigang Yu, José Duato:
Achieving balanced buffer utilization with a proper co-design of flow control and routing algorithm. NOCS 2014: 25-32 - [c100]José V. Escamilla, José Flich, Pedro Javier García:
ICARO: Congestion isolation in networks-on-chip. NOCS 2014: 159-166 - [e2]Giorgos Dimitrakopoulos, Sören Sonntag, José Flich, Pascal Vivet:
Proceedings of the 8th International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC 2014, Vienna, Austria, January 22, 2014. ACM 2014, ISBN 978-1-4503-2639-1 [contents] - 2013
- [j33]Mario Lodde, Antoni Roca, José Flich:
Built-in fast gather control network for efficient support of coherence protocols. IET Comput. Digit. Tech. 7(2) (2013) - [j32]Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato:
Silicon-aware distributed switch architecture for on-chip networks. J. Syst. Archit. 59(7): 505-515 (2013) - [j31]José Flich Cardo, Maurizio Palesi:
Introduction to the special section on on-chip and off-chip network architectures. ACM Trans. Embed. Comput. Syst. 12(4): 104:1-104:2 (2013) - [j30]Alberto Ghiribaldi, Daniele Ludovici, Francisco Triviño, Alessandro Strano, José Flich, José L. Sánchez, Francisco J. Alfaro, Michele Favalli, Davide Bertozzi:
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs. ACM Trans. Embed. Comput. Syst. 12(4): 106:1-106:29 (2013) - [j29]Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato:
An Effective and Feasible Congestion Management Technique for High-Performance MINs with Tag-Based Distributed Routing. IEEE Trans. Parallel Distributed Syst. 24(10): 1918-1929 (2013) - [c99]Mario Lodde, José Flich, Manuel E. Acacio:
Towards Efficient Dynamic LLC Home Bank Mapping with NoC-Level Support. Euro-Par 2013: 178-190 - [c98]María Soler, José Flich:
Power Saving by NoC Traffic Compression. Euro-Par Workshops 2013: 465-476 - [c97]Mario Lodde, José Flich:
A Lightweight Network of IDs to Quickly Deliver Simple Control Messages. Euro-Par Workshops 2013: 477-487 - [c96]Bartosz Bogdanski, Bjørn Dag Johnsen, Sven-Arne Reinemo, José Flich:
Making the Network Scalable: Inter-subnet Routing in InfiniBand. Euro-Par 2013: 685-698 - [c95]Francisco Triviño, Davide Bertozzi, José Flich:
A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs. INA-OCMC@HiPEAC 2013: 1-4 - [c94]José Flich, Scott Pakin, Craig B. Stunkel:
CASS Introduction. IPDPS Workshops 2013: 779-780 - [c93]José V. Escamilla, José Flich, Pedro Javier García:
Head-of-Line Blocking Avoidance in Networks-on-Chip. IPDPS Workshops 2013: 796-805 - [c92]Marco Balboni, Francisco Triviño, José Flich, Davide Bertozzi:
Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms. ISSoC 2013: 1-6 - [c91]Mario Lodde, José Flich:
An NoC and cache hierarchy substrate to address effective virtualization and fault-tolerance. NOCS 2013: 1-8 - [c90]Davide Zoni, José Flich, William Fornaciari:
Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations. PATMOS 2013: 231-234 - [i1]Tomohiro Yoneda, José Flich Cardo, Jiang Xu, Michihiro Koibuchi:
Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8). NII Shonan Meet. Rep. 2013 (2013) - 2012
- [j28]José Flich, Scott Pakin, Craig B. Stunkel:
Special issue on Communication Architectures for Scalable Systems. J. Parallel Distributed Comput. 72(11): 1399-1400 (2012) - [j27]Francisco Triviño, José L. Sánchez, Francisco J. Alfaro, José Flich:
Network-on-Chip virtualization in Chip-Multiprocessor Systems. J. Syst. Archit. 58(3-4): 126-139 (2012) - [j26]Carles Hernández, Antoni Roca, Federico Silla, José Flich, José Duato:
On the Impact of Within-Die Process Variation in GALS-Based NoC Performance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 294-307 (2012) - [j25]José Flich, Tor Skeie, Andres Mejia, Olav Lysne, Pedro López, Antonio Robles, José Duato, Michihiro Koibuchi, Tomas Rokicki, José Carlos Sancho:
A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms. IEEE Trans. Parallel Distributed Syst. 23(3): 405-425 (2012) - [c89]Mario Lodde, José Flich, Manuel E. Acacio:
Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols. Euro-Par 2012: 206-218 - [c88]Albert Esteve, María Soler, María Engracia Gómez, Antonio Robles, José Flich:
Detecting Sharing Patterns in Industrial Parallel Applications for Embedded Heterogeneous Multicore Systems. Euro-Par Workshops 2012: 317-326 - [c87]Antoni Roca, José Flich, Giorgos Dimitrakopoulos:
DESA: Distributed Elastic Switch Architecture for efficient networks-on-FPGAS. FPL 2012: 394-399 - [c86]Mario Lodde, Toni Roca, José Flich:
Heterogeneous network design for effective support of invalidation-based coherency protocols. INA-OCMC@HiPEAC 2012: 1-4 - [c85]Alessandro Strano, Davide Bertozzi, Federico Angiolini, Leonardo Di G. Gregorio, Frank Olaf Sem-Jacobsen, Vladimir Todorov, José Flich, José Silla, Tobias Bjerregaard:
Quest for the ultimate network-on-chip: the NaNoC project. INA-OCMC@HiPEAC 2012: 43-46 - [c84]Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato:
Enabling High-Performance Crossbars through a Floorplan-Aware Design. ICPP 2012: 269-278 - [c83]José Flich, Scott Pakin, Craig B. Stunkel:
CASS Introduction. IPDPS Workshops 2012: 894-895 - [c82]Mario Lodde, José Flich, Manuel E. Acacio:
Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support. NOCS 2012: 59-66 - [c81]Qiaoyan Yu, José Cano, José Flich, Paul Ampadu:
Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip. NOCS 2012: 169-176 - [c80]Francisco Triviño, José L. Sánchez, Francisco José Alfaro, José Flich:
Exploring NoC Virtualization Alternatives in CMPs. PDP 2012: 473-482 - [c79]Alessandro Strano, Davide Bertozzi, Francisco Triviño, José L. Sánchez, Francisco J. Alfaro, José Flich:
OSR-Lite: Fast and deadlock-free NoC reconfiguration framework. ICSAMOS 2012: 86-95 - 2011
- [j24]Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato:
Fault-Tolerant Vertical Link Design for Effective 3D Stacking. IEEE Comput. Archit. Lett. 10(2): 41-44 (2011) - [j23]Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato:
Cost-effective queue schemes for reducing head-of-line blocking in fat-trees. Concurr. Comput. Pract. Exp. 23(17): 2235-2248 (2011) - [j22]Rafael Tornero, Juan Manuel Orduña, Andres Mejia, José Flich, José Duato:
A Communication-Driven Routing Technique for Application-Specific NoCs. Int. J. Parallel Program. 39(3): 357-374 (2011) - [j21]Carles Hernández, Antoni Roca, José Flich, Federico Silla, José Duato:
Characterizing the impact of process variation on 45 nm NoC-based CMPs. J. Parallel Distributed Comput. 71(5): 651-663 (2011) - [j20]Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato:
OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees. J. Parallel Distributed Comput. 71(11): 1460-1472 (2011) - [j19]Francisco Triviño, José L. Sánchez, Francisco José Alfaro, José Flich:
Virtualizing network-on-chip resources in chip-multiprocessors. Microprocess. Microsystems 35(2): 230-245 (2011) - [j18]Antoni Roca, José Flich, Federico Silla, José Duato:
A low-latency modular switch for CMP systems. Microprocess. Microsystems 35(8): 742-754 (2011) - [j17]Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato:
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 534-547 (2011) - [c78]Jesús Camacho Villanueva, José Flich:
HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings. ANCS 2011: 69-80 - [c77]Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Wladek Olesinski:
Towards an Efficient NoC Topology through Multiple Injection Ports. DSD 2011: 165-172 - [c76]Francisco Triviño, Francisco José Alfaro, José L. Sánchez, José Flich:
A fast centralized computation routing algorithm for self-configuring NoC systems. HiPC 2011: 1-10 - [c75]J. Camacho, José Flich, José Duato, Hans Eberle, Wladek Olesinski:
A power-efficient network on-chip topology. INA-OCMC@HiPEAC 2011: 23-26 - [c74]Antoni Roca, Carles Hernández, José Flich, Federico Silla, José Duato:
A Distributed Switch Architecture for On-Chip Networks. ICPP 2011: 21-30 - [c73]Jesús Camacho Villanueva, José Flich, Antoni Roca, José Duato:
PC-Mesh: A Dynamic Parallel Concentrated Mesh. ICPP 2011: 642-651 - [c72]Jesús Escudero-Sahuquillo, Ernst Gunnar Gran, Pedro Javier García, José Flich, Tor Skeie, Olav Lysne, Francisco J. Quiles, José Duato:
Combining Congested-Flow Isolation and Injection Throttling in HPC Interconnection Networks. ICPP 2011: 662-672 - [c71]José Flich, Scott Pakin, Craig B. Stunkel:
CASS Introduction. IPDPS Workshops 2011: 716-717 - [c70]Francisco Triviño, Francisco José Alfaro, José L. Sánchez, José Flich:
NoC Reconfiguration for CMP Virtualization. NCA 2011: 219-222 - [c69]José Cano, José Flich, José Duato, Marcello Coppola, Riccardo Locatelli:
Efficient routing implementation in complex systems-on-chip. NOCS 2011: 1-8 - [c68]Florentine Dubois, José Cano, Marcello Coppola, José Flich, Frédéric Pétrot:
Spidergon STNoC design flow. NOCS 2011: 267-268 - [e1]José Flich, Davide Bertozzi, Tor Skeie, Daniele Ludovici:
Proceedings of the Fifth International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC '11, Heraklion, Greece, January 23, 2011. ACM 2011, ISBN 978-1-4503-0272-2 [contents] - [r2]José Flich:
Flow Control. Encyclopedia of Parallel Computing 2011: 683-689 - [r1]José Flich:
Switch Architecture. Encyclopedia of Parallel Computing 2011: 1971-1977 - 2010
- [j16]Teresa Nachiondo Frinós, José Flich, José Duato:
Buffer Management Strategies to Reduce HoL Blocking. IEEE Trans. Parallel Distributed Syst. 21(6): 739-753 (2010) - [c67]Antoni Roca, José Flich, Federico Silla, José Duato:
A Latency-Efficient Router Architecture for CMP Systems. DSD 2010: 165-172 - [c66]José Flich, Alfonso Urso, Ulrich Brüning, Giuseppe Di Fatta:
High Performance Networks. Euro-Par (2) 2010: 412 - [c65]Antoni Roca, José Flich, Federico Silla, José Duato:
VCTlite: Towards an efficient implementation of virtual cut-through switching in on-chip networks. HiPC 2010: 1-12 - [c64]Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato:
Cost-Effective Congestion Management for Interconnection Networks Using Distributed Deterministic Routing. ICPADS 2010: 355-364 - [c63]Scott Pakin, Craig B. Stunkel, José Flich, Henrique Andrade, Vibhore Kumar, Deepak S. Turaga:
Welcome to CAC/SSPS 2010. IPDPS Workshops 2010: 1 - [c62]Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesús Camacho Villanueva, Federico Silla, José Duato:
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. NOCS 2010: 25-32 - [c61]Carles Hernández, Antoni Roca, Federico Silla, José Flich, José Duato:
Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. NOCS 2010: 35-42
2000 – 2009
- 2009
- [j15]Samuel Rodrigo, Simone Medardoni, José Flich, Davide Bertozzi, José Duato:
Efficient implementation of distributed routing algorithms for NoCs. IET Comput. Digit. Tech. 3(5): 460-475 (2009) - [j14]Alejandro Martínez, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, José Flich, Francisco J. Quiles, José Duato:
A Switch Architecture Guaranteeing QoS Provision and HOL Blocking Elimination. IEEE Trans. Parallel Distributed Syst. 20(1): 13-24 (2009) - [j13]Andres Mejia, Maurizio Palesi, José Flich, Shashi Kumar, Pedro López, Rickard Holsmark, José Duato:
Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. IEEE Trans. Very Large Scale Integr. Syst. 17(3): 356-369 (2009) - [c60]Vicente Chirivella, Rosa Alcover, José Flich, José Duato:
Dependability Analysis of a Fault-Tolerant Network Reconfiguring Strategy. Euro-Par 2009: 1040-1051 - [c59]Tor Skeie, Frank Olaf Sem-Jacobsen, Samuel Rodrigo, José Flich, Davide Bertozzi, Simone Medardoni:
Flexible DOR routing for virtualization of multicore chips. SoC 2009: 73-76 - [c58]Samuel Rodrigo, Carles Hernández, José Flich, Federico Silla, José Duato, Simone Medardoni, Davide Bertozzi, Andres Mejia, Donglai Dai:
Yield-oriented evaluation methodology of network-on-chip routing implementations. SoC 2009: 100-105 - [c57]Jesús Camacho Villanueva, José Flich, José Duato, Hans Eberle, Nils Gura, Wladek Olesinski:
A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors. NoCArc@MICRO 2009: 51-56 - 2008
- [j12]José Flich, José Duato:
Logic-Based Distributed Routing for NoCs. IEEE Comput. Archit. Lett. 7(1): 13-16 (2008) - [j11]José Flich, Samuel Rodrigo, José Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne:
On the Potential of NoC Virtualization for Multicore Chips. Scalable Comput. Pract. Exp. 9(3) (2008) - [j10]Olav Lysne, José Miguel Montañana, José Flich, José Duato, Timothy Mark Pinkston, Tor Skeie:
An Efficient and Deadlock-Free Network Reconfiguration Protocol. IEEE Trans. Computers 57(6): 762-779 (2008) - [c56]José Flich, Samuel Rodrigo, José Duato, Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Olav Lysne:
On the Potential of NoC Virtualization for Multicore Chips. CISIS 2008: 801-807 - [c55]Rafael Tornero, Juan Manuel Orduña, Andres Mejia, José Flich, José Duato:
CART: Communication-Aware Routing Technique for Application-Specific NoCs. DSD 2008: 26-31 - [c54]Tor Skeie, Daniel Ortega, José Flich, Raimir Holanda:
Topic 13: High-Performance Networks. Euro-Par 2008: 898 - [c53]Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco J. Quiles, José Flich, José Duato:
FBICM: Efficient Congestion Management for High-Performance Networks Using Distributed Deterministic Routing. HiPC 2008: 503-517 - [c52]Andres Mejia, José Flich, José Duato:
On the Potentials of Segment-Based Routing for NoCs. ICPP 2008: 594-603 - [c51]José Miguel Montañana, José Flich, José Duato:
Epoch-based reconfiguration: Fast, simple, and effective dynamic network reconfiguration. IPDPS 2008: 1-12 - [c50]Samuel Rodrigo, José Flich, José Duato, Mark Hummel:
Efficient unicast and multicast support for CMPs. MICRO 2008: 364-375 - [c49]José Flich, Samuel Rodrigo, José Duato:
An Efficient Implementation of Distributed Routing Algorithms for NoCs. NOCS 2008: 87-96 - [c48]Hans Eberle, Pedro Javier García, José Flich, José Duato, Robert J. Drost, Nils Gura, David Hopkins, Wladek Olesinski:
High-radix crossbar switches enabled by proximity communication. SC 2008: 32 - 2007
- [c47]Alejandro Martínez-Vicente, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, José Flich, Francisco J. Quiles, José Duato:
Integrated QoS Provision and Congestion Management for Interconnection Networks. Euro-Par 2007: 837-847 - [c46]Gaspar Mora, Pedro Javier García, José Flich, José Duato:
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management. ICPP 2007: 74 - [c45]José Flich, Andres Mejia, Pedro López, José Duato:
Region-Based Routing: An Efficient Routing Mechanism to Tackle Unreliable Hardware in Network on Chips. NOCS 2007: 183-194 - [c44]Andres Mejia, José Flich, José Duato, Sven-Arne Reinemo, Tor Skeie:
Boosting Ethernet Performance by Segment-Based Routing. PDP 2007: 55-62 - [c43]Leticia Pascual, Alejandro Torrentí, Julio Sahuquillo, José Flich:
Understanding cache hierarchy interactions with a program-driven simulator. WCAE 2007: 30-35 - 2006
- [j9]Pedro Javier García, Francisco J. Quiles, José Flich, José Duato, Ian Johnson, Finbar Naven:
Efficient, Scalable Congestion Management for Interconnection Networks. IEEE Micro 26(5): 52-66 (2006) - [j8]María Engracia Gómez, Nils Agne Nordbotten, José Flich, Pedro López, Antonio Robles, José Duato, Tor Skeie, Olav Lysne:
A Routing Methodology for Achieving Fault Tolerance in Direct Networks. IEEE Trans. Computers 55(4): 400-415 (2006) - [c42]Gaspar Mora, José Flich, José Duato, Pedro López, Elvira Baydal, Olav Lysne:
Towards an efficient switch architecture for high-radix switches. ANCS 2006: 11-20 - [c41]Alejandro Martínez, Pedro Javier García, Francisco José Alfaro, José L. Sánchez, José Flich, Francisco J. Quiles, José Duato:
Towards a Cost-Effective Interconnection Network Architecture with QoS and Congestion Management Support. Euro-Par 2006: 884-895 - [c40]Teresa Nachiondo Frinós, José Flich, José Duato:
Destination-Based HoL Blocking Elimination. ICPADS (1) 2006: 213-222 - [c39]José Miguel Montañana, José Flich, Antonio Robles, José Duato:
Reachability-Based Fault-Tolerant Routing. ICPADS (1) 2006: 515-524 - [c38]Pedro Javier García, Francisco J. Quiles, José Flich, José Duato, Ian Johnson, Finbar Naven:
RECN-DD: A Memory-Efficient Congestion Management Technique for Advanced Switching. ICPP 2006: 23-32 - [c37]Andres Mejia, José Flich, José Duato, Sven-Arne Reinemo, Tor Skeie:
Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and tori. IPDPS 2006 - 2005
- [j7]Michihiro Koibuchi, Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato:
Enforcing in-order packet delivery in system area networks with adaptive routing. J. Parallel Distributed Comput. 65(10): 1223-1236 (2005) - [c36]Teresa Nachiondo Frinós, José Flich, José Duato, Mitchell Gusat:
Cost / Performance Trade-Offs and Fairness Evaluation of Queue Mapping Policies. Euro-Par 2005: 1024-1034 - [c35]Pedro Javier García, José Flich, José Duato, Francisco J. Quiles, Ian Johnson, Finbar Naven:
On the Correct Sizing on Meshes Through an Effective Congestion Management Strategy. Euro-Par 2005: 1035-1045 - [c34]Pedro Javier García, José Flich, José Duato, Ian Johnson, Francisco J. Quiles, Finbar Naven:
Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture. HiPEAC 2005: 266-285 - [c33]José Duato, Ian Johnson, José Flich, Finbar Naven, Pedro Javier García, Teresa Nachiondo Frinós:
A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks. HPCA 2005: 108-119 - [c32]Teresa Nachiondo Frinós, José Flich, José Duato:
Efficient Reduction of HOL Blocking in Multistage Networks. IPDPS 2005 - [c31]Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato, Michihiro Koibuchi:
In-Order Packet Delivery in Interconnection Networks using Adaptive Routing. IPDPS 2005 - [c30]José Miguel Montañana, José Flich, Antonio Robles, José Duato:
A Scalable Methodology for Computing Fault-Free Paths in InfiniBand Torus Networks. ISHPC 2005: 79-92 - [c29]Raúl Martínez, José L. Sánchez, Francisco José Alfaro, Vicente Chirivella, José Flich:
Studying the Effect of the Design Parameters on the Interconnection Network Performance in NOWs. PDP 2005: 102-109 - 2004
- [j6]María Engracia Gómez, José Duato, José Flich, Pedro López, Antonio Robles, Nils Agne Nordbotten, Olav Lysne, Tor Skeie:
An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori. IEEE Comput. Archit. Lett. 3 (2004) - [j5]Jeffrey M. Stine, Nicholas P. Carter, José Flich:
Comparing Adaptive Routing and Dynamic Voltage Scaling for Link Power Reduction. IEEE Comput. Archit. Lett. 3 (2004) - [c28]María Engracia Gómez, José Duato, José Flich, Pedro López, Antonio Robles, Nils Agne Nordbotten, Tor Skeie, Olav Lysne:
A New Adaptive Fault-Tolerant Routing Methodology for Direct Networks. HiPC 2004: 462-473 - [c27]Olav Lysne, José Miguel Montañana, Timothy Mark Pinkston, José Duato, Tor Skeie, José Flich:
Simple Deadlock-Free Dynamic Network Reconfiguration. HiPC 2004: 504-515 - [c26]Tor Skeie, Olav Lysne, José Flich, Pedro López, Antonio Robles, José Duato:
LASH-TOR: A Generic Transition-Oriented Routing Algorithm. ICPADS 2004: 595-604 - [c25]María Engracia Gómez, José Flich, Pedro López, Antonio Robles, José Duato, Nils Agne Nordbotten, Olav Lysne, Tor Skeie:
An Effective Fault-Tolerant Routing Methodology for Direct Networks. ICPP 2004: 222-231 - [c24]José Miguel Montañana, José Flich, Antonio Robles, Pedro López, José Duato:
A Transition-Based Fault-Tolerant Routing Methodology for InfiniBand Networks. IPDPS 2004 - [c23]Nils Agne Nordbotten, María Engracia Gómez, José Flich, Pedro López, Antonio Robles, Tor Skeie, Olav Lysne, José Duato:
A Fully Adaptive Fault-Tolerant Routing Methodology Based on Intermediate Nodes. NPC 2004: 341-356 - [c22]José Duato, José Flich, Teresa Nachiondo Frinós:
A Cost-Effective Technique to Reduce HOL Blocking in Single-Stage and Multistage Switch Fabrics. PDP 2004: 48-53 - 2003
- [j4]Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato:
Supporting adaptive routing in IBA switches. J. Syst. Archit. 49(10-11): 441-456 (2003) - [j3]José Flich, Pedro López, Manuel P. Malumbres, José Duato, Tomas Rokicki:
Applying In-Transit Buffers to Boost the Performance of Networks with Source Routing. IEEE Trans. Computers 52(9): 1134-1153 (2003) - [c21]Pedro López, José Flich, Antonio Robles:
Low-Fragmentation Mapping Strategies for Linear Forwarding Tables in InfiniBandTM. Euro-Par 2003: 947-957 - [c20]José Carlos Sancho, Antonio Robles, Pedro López, José Flich, José Duato:
Routing in InfiniBandTM Torus Network Topologie. ICPP 2003: 509-518 - [c19]Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato:
Supporting Fully Adaptive Routing in InfiniBand Networks. IPDPS 2003: 44 - [c18]María Engracia Gómez, José Flich, Antonio Robles, Pedro López, José Duato:
VOQSW: A Methodology to Reduce HOL Blocking in InfiniBand Networks. IPDPS 2003: 46 - [c17]José Carlos Sancho, Juan Carlos Martínez, Antonio Robles, Pedro López, José Flich, José Duato:
Performance Evaluation of COWs under Real Parallel Application. IPDPS 2003: 202 - [c16]Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato:
Supporting Adaptive Routing in InfiniBand Networks. PDP 2003: 165-172 - 2002
- [j2]José Flich, Pedro López, Manuel P. Malumbres, José Duato:
Boosting the Performance of Myrinet Networks. IEEE Trans. Parallel Distributed Syst. 13(7): 693-709 (2002) - [j1]José Flich, Pedro López, Manuel P. Malumbres, José Duato:
Boosting the Performance of Myrinet Networks. IEEE Trans. Parallel Distributed Syst. 13(11): 1166-1182 (2002) - [c15]María Engracia Gómez, José Flich, Antonio Robles, Pedro López, José Duato:
Evaluation of Routing Algorithms for InfiniBand Networks (Research Note). Euro-Par 2002: 775-780 - [c14]José Carlos Sancho, Antonio Robles, José Flich, Pedro López, José Duato:
Effective Methodology for Deadlock-Free Minimal Routing in InfiniBand Networks. ICPP 2002: 409-418 - [c13]Pedro Javier García, M. D. Mora, Francisco José Alfaro, José L. Sánchez, José Flich:
Evaluation of Alternative Arbitration Policies for Myrinet Switches. IPDPS 2002 - [c12]José Carlos Sancho, José Flich, Antonio Robles, Pedro López, José Duato:
Analyzing the Influence of Virtual Lanes on the Performance of InfiniBand Networks. IPDPS 2002 - [c11]José Flich, Pedro López, José Carlos Sancho, Antonio Robles, José Duato:
Improving InfiniBand Routing through Multiple Virtual Networks. ISHPC 2002: 49-63 - [c10]José Flich, Manuel P. Malumbres, Pedro López, José Duato:
Removing the Latency Overhead of the ITB Mechanism in COWs with Source Routing. PDP 2002: 463-470 - 2001
- [c9]Pedro López, José Flich, José Duato:
Deadlock-Free Routing in InfiniBand through Destination Renaming. ICPP 2001: 427-436 - [c8]José Flich, Pedro López, Manuel P. Malumbres, José Duato, Tomas Rokicki:
Improving Network Performance by Reducing Network Contention in Source-Based COWs with a Low Path-Computation Overhead. IPDPS 2001: 70 - [c7]Salvador Coll, José Flich, Manuel P. Malumbres, Pedro López, José Duato, Francisco J. Mora:
A First Implementation of In-Transit Buffers on Myrinet GM Software. IPDPS 2001: 162 - 2000
- [c6]José Flich, Pedro López, Manuel P. Malumbres, José Duato:
Improving the Performance of Regular Networks with Source Routing. ICPP 2000: 353-361 - [c5]José Flich, Manuel P. Malumbres, Pedro López, José Duato:
Performance evaluation of a new routing strategy for irregular networks with source routing. ICS 2000: 34-43 - [c4]José Flich, Manuel P. Malumbres, Pedro López, José Duato:
Improving Routing Performance in Myrinet Networks. IPDPS 2000: 27-32 - [c3]José Flich, Pedro López, Manuel P. Malumbres, José Duato, Tomas Rokicki:
Combining In-Transit Buffers with Optimized Routing Schemes to Boost the Performance of Networks with Source Routing. ISHPC 2000: 300-309
1990 – 1999
- 1999
- [c2]José Flich, Manuel P. Malumbres, Pedro López, José Duato:
Performance Evaluation of Networks of Workstations with Hardware Shared Memory Model Using Execution-Driven Simulation. ICPP 1999: 146-153 - 1998
- [c1]José Flich, Pedro López, Manuel P. Malumbres, José Duato:
Edinet: An Execution Driven Interconnection Network Simulator for DSM Systems. Computer Performance Evaluation (Tools) 1998: 336-339
Coauthor Index
Francisco J. Alfaro
aka: Francisco José Alfaro
aka: Francisco J. Alfaro-Cortes
aka: Francisco J. Alfaro-Cortés
aka: Francisco José Alfaro
aka: Francisco J. Alfaro-Cortes
aka: Francisco J. Alfaro-Cortés
[j50] [j49] [j48] [i3] [c118] [j37] [j35] [c101] [j32] [j29] [j26] [j25] [c84] [j24] [j23] [j22] [j21] [j20] [j18] [j17] [c77] [c75] [c74] [c73] [c72] [c69] [j16] [c67] [c65] [c64] [c62] [c61] [j15] [j14] [j13] [c60] [c58] [c57] [j12] [j11] [j10] [c56] [c55] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [j9] [j8] [c42] [c41] [c40] [c39] [c38] [c37] [j7] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [j6] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [j4] [j3] [c20] [c19] [c18] [c17] [c16] [j2] [j1] [c15] [c14] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
Carles Hernández 0001
aka: Carles Hernández Luz
aka: Carles Hernández Luz
Rafael Tornero
aka: Rafael Tornero Gavilá
aka: Rafael Tornero Gavilá
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