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ORCIDHiroki Koike
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2020 – today
- 2022
[c12]K. Watanabe, T. Shimada, K. Hirose, H. Shindo, D. Kobayashi, Takaho Tanigawa, Shoji Ikeda
, Takamitsu Shinada, Hiroki Koike, Tetsuo Endoh, T. Makino, Takeshi Ohshima:
Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability. IRPS 2022: 54-1
2010 – 2019
- 2019
- [j12]Hiroki Koike, István Kovács, Dragan Marusic, Mikhail E. Muzychuk:
Cyclic groups are CI-groups for balanced configurations. Des. Codes Cryptogr. 87(6): 1227-1235 (2019) - [j11]Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits 54(11): 2991-3004 (2019) - [c11]Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC 2019: 202-204 - [c10]Ryo Tamura, N. Watanabe, Hiroki Koike, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Soshi Sato:
A novel memory test system with an electromagnet for STT-MRAM testing. NVMTS 2019: 1-4 - 2018
- [c9]Ryo Tamura, I. Mori, N. Watanabe, Hiroki Koike, Tetsuo Endoh:
Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system. NVMTS 2018: 1-5 - 2017
- [j10]Hiroki Koike, Daniel Pellicer, Miguel Raggi, Steve Wilson:
Flag Bicolorings, Pseudo-Orientations, and Double Covers of Maps. Electron. J. Comb. 24(1): 1 (2017) - 2016
- [j9]Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno:
An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(2): 109-119 (2016) - [j8]Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno:
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104(10): 1844-1863 (2016) - [c8]Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS 2016: 1878-1881 - 2014
- [j7]Hiroki Koike, István Kovács:
Isomorphic tetravalent cyclic Haar graphs. Ars Math. Contemp. 7(1): 215-235 (2014) - 2013
- [j6]Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh:
A 1 Mb Nonvolatile Embedded Memory Using 4T2MTJ Cell With 32 b Fine-Grained Power Gating Scheme. IEEE J. Solid State Circuits 48(6): 1511-1520 (2013) - 2012
- [c7]Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh:
High-speed simulator including accurate MTJ models for spintronics integrated circuit design. ISCAS 2012: 1971-1974 - [c6]Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh:
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times. VLSIC 2012: 46-47 - 2011
- [j5]Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura:
An Electrically Adjustable 3-Terminal Regulator for Post-Fabrication Level-Trimming with a Reliable 1-Wire Serial I/O. IEICE Trans. Electron. 94-C(6): 945-952 (2011) - 2010
- [c5]Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura:
An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function. ASP-DAC 2010: 365-366
2000 – 2009
- 2002
- [j4]Junichi Yamada, Tohru Miwa, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Hidemitsu Mori, Seiichi Takahashi, Hidenori Takeuchi, Takemitsu Kunio:
A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers. IEEE J. Solid State Circuits 37(8): 1073-1079 (2002) - 2001
- [j3]Tohru Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiko Maejima, Hiromitsu Hada, Takemitsu Kunio:
NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors. IEEE J. Solid State Circuits 36(3): 522-527 (2001) - [c4]Hideo Toyoshima, Sota Kobayashi, Junichi Yamada, Tohru Miwa, Hiroki Koike, Hidenori Takeuchi, Hidemitsu Mori, Naoki Kasai, Yukihiko Maejima, Nobuhira Tanabe, Toru Tatsumi, Hiromitsu Hada:
FeRAM device and circuit technologies fully compatible with advanced CMOS. CICC 2001: 171-178 - 2000
- [c3]Tohm Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Tom Tatsumi, Yukihiro Maejima, Hiromitsu Hada, Takemitsu Kunio:
NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors. CICC 2000: 65-68
1990 – 1999
- 1998
- [c2]Tohru Miwa, Junichi Yamada, Yuji Okamoto, Hiroki Koike, Hideo Toyoshiina, Hiromitsu Hada, Yoshihiro Hayashi, Hiroaki Oliizaki, Yoichi Miyasalca, Takemitsu Kunio, Hidenobu Miyamoto, Hideki Gomi, Hiroshi Kitajima:
An embedded FeRAM macro cell for a smart card microcontroller. CICC 1998: 439-442 - 1992
- [j2]Akira Tanabe, Toshio Takeshima, Hiroki Koike, Yoshiharu Aimoto, Masahide Takada, Toshiyuki Ishijima, Naoki Kasai, Hiromitsu Hada, Kentaro Shibahara, Takemitsu Kunio, Takaho Tanigawa, Takanori Saeki, Masato Sakao, Hidenobu Miyamoto, Hiroshi Nozue, Shuichi Ohya, Tatsunori Murotani, Kuniaki Koyama, Takashi Okuda:
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function. IEEE J. Solid State Circuits 27(11): 1525-1533 (1992) - 1990
- [j1]Toshio Takeshima, Masahide Takada, Hiroki Koike, Hiroshi Watanabe, Shigeru Koshimaru, Kenjiro Mitake, Wataru Kikuchi, Takaho Tanigawa, Tatsunori Murotani, Kenji Noda, Kazuhiro Tasaka, Koji Yamanaka, Kuniaki Koyama:
A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM. IEEE J. Solid State Circuits 25(4): 903-911 (1990) - [c1]Hiroki Koike, Toshio Takeshima, Masahide Takada:
A BIST scheme using microprogram ROM for large capacity memories. ITC 1990: 815-822
Coauthor Index
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