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ORCIDSandip Kundu
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- affiliation: University of Massachusetts Amherst, USA
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2020 – today
- 2024
[j69]Dong Hyub Kim
, Jonah O'Brien Weiss, Sandip Kundu:
Extracting DNN Architectures via Runtime Profiling on Mobile GPUs. IEEE J. Emerg. Sel. Topics Circuits Syst. 14(4): 620-633 (2024)- [j68]Chandra Sekhar Mummidi, Victor da Cruz Ferreira, Sudarshan Srinivasan, Sandip Kundu:
Highly Efficient Self-checking Matrix Multiplication on Tiled AMX Accelerators. ACM Trans. Archit. Code Optim. 21(2): 21 (2024) - [c192]Bharadwaj Madabhushi, Sandip Kundu, Daniel E. Holcomb:
Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes. DATE 2024: 1-6 - [c191]Chandra Sekhar Mummidi, Sandeep Bal, Sandip Kundu:
A Novel Self-Repair Mechanism for Tiled Matrix Multiplication Unit. DFT 2024: 1-6 - [c190]Bharadwaj Madabhushi, Chandra Sekhar Mummidi, Sandip Kundu, Daniel E. Holcomb:
Resurrection Attack: Defeating Xilinx MPU's Memory Protection. HOST 2024: 394-403 - [c189]Zhehang Zhang, Bharadwaj Madabhushi, Sandip Kundu, Russell Tessier:
Security Risks Due to Data Persistence in Cloud FPGA Platforms. MWSCAS 2024: 1398-1402 - [i8]Bharadwaj Madabhushi, Sandip Kundu, Daniel E. Holcomb:
Memory Scraping Attack on Xilinx FPGAs: Private Data Extraction from Terminated Processes. CoRR abs/2405.13927 (2024) - [i7]Bharadwaj Madabhushi, Chandra Sekhar Mummidi, Sandip Kundu, Daniel E. Holcomb:
Resurrection Attack: Defeating Xilinx MPU's Memory Protection. CoRR abs/2405.13933 (2024) - [i6]Zhehang Zhang, Bharadwaj Madabhushi, Sandip Kundu, Russell Tessier:
Security Risks Due to Data Persistence in Cloud FPGA Platforms. CoRR abs/2408.10374 (2024) - 2023
- [j67]Chandra Sekhar Mummidi, Sandip Kundu:
ACTION: Adaptive Cache Block Migration in Distributed Cache Architectures. ACM Trans. Archit. Code Optim. 20(2): 25:1-25:19 (2023) - [c188]Sandeep Bal, Chandra Sekhar Mummidi, Victor da Cruz Ferreira, Sudarshan Srinivasan, Sandip Kundu:
A Novel Fault-Tolerant Architecture for Tiled Matrix Multiplication. DATE 2023: 1-6 - [c187]Chandra Sekhar Mummidi, Sandip Kundu:
A Neural Network-Based Approach to Dynamic Core Morphing for AMPs. iSES 2023: 4-9 - [c186]Hanmei Yang, Xin Zhao, Jin Zhou, Wei Wang, Sandip Kundu, Bo Wu, Hui Guan, Tongping Liu:
NUMAlloc: A Faster NUMA Memory Allocator. ISMM 2023: 97-110 - [i5]Jonah O'Brien Weiss, Tiago A. O. Alves, Sandip Kundu:
EZClone: Improving DNN Model Extraction Attack via Shape Distillation from GPU Execution Profiles. CoRR abs/2304.03388 (2023) - 2022
- [j66]Manaar Alam, Sayandeep Saha, Debdeep Mukhopadhyay, Sandip Kundu:
NN-Lock: A Lightweight Authorization to Prevent IP Threats of Deep Learning Models. ACM J. Emerg. Technol. Comput. Syst. 18(3): 51:1-51:19 (2022) - [j65]Vinay C. Patil, Sandip Kundu:
Realizing Robust, Lightweight Strong PUFs for Securing Smart Grids. IEEE Trans. Consumer Electron. 68(1): 5-13 (2022) - [j64]Md. Nazmul Islam, Sandip Kundu:
Remote Device Management via Smart Contracts. IEEE Trans. Consumer Electron. 68(1): 38-46 (2022) - [c185]Jonah O'Brien Weiss, Tiago A. O. Alves, Sandip Kundu:
Hardening DNNs against Transfer Attacks during Network Compression using Greedy Adversarial Pruning. AICAS 2022: 324-327 - [c184]Chandra Sekhar Mummidi, Sandeep Bal, Brunno F. Goldstein, Sudarshan Srinivasan, Sandip Kundu:
A Highly-Efficient Error Detection Technique for General Matrix Multiplication using Tiled Processing on SIMD Architecture. ICCD 2022: 529-536 - [c183]Md. Nazmul Islam, Sandip Kundu:
A Software Approach Towards Defeating Power Management Side Channel Leakage. IOLTS 2022: 1-7 - [c182]Victor da Cruz Ferreira, Sandip Kundu, Felipe M. G. França:
Analysis of Fake News Classification for Insight into the Roles of Different Data Types. ICSC 2022: 75-82 - [c181]Victor da Cruz Ferreira, Haitham H. Esmat, Beatriz Lorenzo, Sandip Kundu, Felipe M. G. França:
Reinforcement Learning based Multi-Attribute Slice Admission Control for Next-Generation Networks in a Dynamic Pricing Environment. VTC Spring 2022: 1-5 - [i4]Jonah O'Brien Weiss, Tiago A. O. Alves, Sandip Kundu:
Hardening DNNs against Transfer Attacks during Network Compression using Greedy Adversarial Pruning. CoRR abs/2206.07406 (2022) - 2021
- [j63]Brunno F. Goldstein, Vinay C. Patil, Victor da Cruz Ferreira, Alexandre Solon Nery, Felipe M. G. França, Sandip Kundu:
Preventing DNN Model IP Theft via Hardware Obfuscation. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 267-277 (2021) - [j62]Tiago A. O. Alves, Leandro A. J. Marzulo, Sandip Kundu, Felipe M. G. França:
Concurrency Analysis in Dynamic Dataflow Graphs. IEEE Trans. Emerg. Top. Comput. 9(1): 44-54 (2021) - [c180]Jonathan Ponader, Kyle Thomas, Sandip Kundu, Yan Solihin:
MILR: Mathematically Induced Layer Recovery for Plaintext Space Error Correction of CNNs. DSN 2021: 75-87 - [c179]Brunno F. Goldstein, Victor da Cruz Ferreira, Sudarshan Srinivasan, Dipankar Das, Alexandre Solon Nery, Sandip Kundu, Felipe M. G. França:
A Lightweight Error-Resiliency Mechanism for Deep Neural Networks. ISQED 2021: 311-316 - 2020
- [j61]Leandro Santiago, Letícia Dias Verona, Fábio Medeiros Rangel, Fabrício Firmino de Faria, Daniel S. Menasché, Wouter Caarls, Maurício Breternitz Jr., Sandip Kundu, Priscila M. V. Lima, Felipe M. G. França:
Weightless Neural Networks as Memory Segmented Bloom Filters. Neurocomputing 416: 292-304 (2020) - [c178]Leandro Santiago de Araújo, Leandro A. J. Marzulo, Tiago A. O. Alves, Felipe M. G. França, Israel Koren, Sandip Kundu:
Building a portable deeply-nested implicit information flow tracking. CF 2020: 150-157 - [c177]Tiago A. O. Alves, Sandip Kundu:
Towards Adversarial Attack Resistant Deep Neural Networks. ESANN 2020: 49-54 - [c176]Irith Pomeranz, Sandip Kundu:
Reduced Fault Coverage as a Target for Design Scaffolding Security. IOLTS 2020: 1-6 - [c175]Vinay C. Patil, Sandip Kundu:
On Leveraging Multi-threshold FinFETs for Design Obfuscation. ISVLSI 2020: 108-113 - [c174]Brunno F. Goldstein, Sudarshan Srinivasan, Dipankar Das, Kunal Banerjee, Leandro Santiago de Araújo, Victor da Cruz Ferreira, Alexandre Solon Nery, Sandip Kundu, Felipe M. G. França:
Reliability Evaluation of Compressed Deep Learning Models. LASCAS 2020: 1-5 - [p1]Md. Nazmul Islam, Sandip Kundu:
IoT Security, Privacy and Trust in Home-Sharing Economy via Blockchain. Blockchain Cybersecurity, Trust and Privacy 2020: 33-50 - [i3]Manaar Alam, Sayandeep Saha, Debdeep Mukhopadhyay, Sandip Kundu:
Deep-Lock: Secure Authorization for Deep Neural Networks. CoRR abs/2008.05966 (2020) - [i2]Jonathan Ponader, Sandip Kundu, Yan Solihin:
MILR: Mathematically Induced Layer Recovery for Plaintext Space Error Correction of CNNs. CoRR abs/2010.14687 (2020)
2010 – 2019
- 2019
- [j60]Leandro Santiago de Araújo, Vinay C. Patil, Charles B. Prado, Tiago A. O. Alves, Leandro A. J. Marzulo, Felipe M. G. França, Sandip Kundu:
Design of Robust, High-Entropy Strong PUFs via Weightless Neural Network. J. Hardw. Syst. Secur. 3(3): 235-249 (2019) - [j59]Md. Nazmul Islam, Sandip Kundu:
Enabling IC Traceability via Blockchain Pegged to Embedded PUF. ACM Trans. Design Autom. Electr. Syst. 24(3): 36:1-36:23 (2019) - [c173]Leandro Santiago de Araújo, Vinay C. Patil, Leandro Augusto Justen Marzulo, Felipe Maia Galvão França, Sandip Kundu:
Efficient Testing of Physically Unclonable Functions for Uniqueness. ATS 2019: 117-122 - [c172]Md. Nazmul Islam, Sandip Kundu:
Remote Configuration of Integrated Circuit Features and Firmware Management via Smart Contract. Blockchain 2019: 325-331 - [c171]Leandro Santiago de Araújo, Victor da Cruz Ferreira, Brunno Figueiroa Goldstein, Alexandre Solon Nery, Leandro Augusto Justen Marzulo, Sandip Kundu, Felipe Maia Galvão França:
Hardware-Accelerated Similarity Search with Multi-Index Hashing. DASC/PiCom/DataCom/CyberSciTech 2019: 733-740 - [c170]Leandro Santiago de Araújo, Letícia Dias Verona, Fábio Medeiros Rangel, Fabrício Firmino de Faria, Daniel Sadoc Menasché, Wouter Caarls, Maurício Breternitz, Sandip Kundu, Priscila Machado Vieira Lima, Felipe Maia Galvão França:
Memory Efficient Weightless Neural Network using Bloom Filter. ESANN 2019 - [c169]Pascal Andreas Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. ESSCIRC 2019: 1-4 - [c168]Tiago A. O. Alves, Felipe M. G. França, Sandip Kundu:
MLPrivacyGuard: Defeating Confidence Information based Model Inversion Attacks on Machine Learning Systems. ACM Great Lakes Symposium on VLSI 2019: 411-415 - [c167]Sandip Kundu:
MPP Keynote 1. IPDPS Workshops 2019: 808 - [i1]Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, Sandip Kundu:
Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device- and Logic-Level Techniques. CoRR abs/1910.00981 (2019) - 2018
- [j58]Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu:
On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(3): 960-969 (2018) - [c166]Horacio L. França, Charles B. Prado, Vinay C. Patil, Sandip Kundu:
Defeating Strong PUF Modeling Attack via Adverse Selection of Challenge-Response Pairs. AsianHOST 2018: 25-30 - [c165]Md. Nazmul Islam, Sandip Kundu:
PMU-Trojan: On exploiting power management side channel for information leakage. ASP-DAC 2018: 709-714 - [c164]Anderson Luiz Sartor, Arthur Francisco Lorenzon, Sandip Kundu, Israel Koren, Antonio C. S. Beck:
Adaptive and polymorphic VLIW processor to optimize fault tolerance, energy consumption, and performance. CF 2018: 54-61 - [c163]Arman Pouraghily, Md. Nazmul Islam, Sandip Kundu, Tilman Wolf:
Poster Abstract: Privacy in Blockchain-Enabled IoT Devices. IoTDI 2018: 292-293 - [c162]Md. Nazmul Islam, Sandip Kundu:
Poster Abstract: Preserving IoT Privacy in Sharing Economy Via Smart Contract. IoTDI 2018: 296-297 - [c161]Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu:
On IC traceability via blockchain. VLSI-DAT 2018: 1-4 - 2017
- [j57]Arunkumar Vijayakumar, Vinay C. Patil, Daniel E. Holcomb, Christof Paar, Sandip Kundu:
Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques. IEEE Trans. Inf. Forensics Secur. 12(1): 64-77 (2017) - [j56]Anirban Sengupta, Sandip Kundu:
Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3265-3267 (2017) - [c160]Tiago A. O. Alves, Sandip Kundu, Leandro A. J. Marzulo, Felipe M. G. França:
A resilient scheduler for dataflow execution. DFT 2017: 1-4 - [c159]Leandro Santiago, Vinay C. Patil, Charles B. Prado, Tiago A. O. Alves, Leandro A. J. Marzulo, Felipe M. G. França, Sandip Kundu:
Realizing strong PUF from weak PUF via neural computing. DFT 2017: 1-6 - [c158]Vinay C. Patil, Arunkumar Vijayakumar, Daniel E. Holcomb, Sandip Kundu:
Improving reliability of weak PUFs via circuit techniques to enhance mismatch. HOST 2017: 146-150 - [c157]Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu:
A guide to graceful aging: How not to overindulge in post-silicon burn-in for enhancing reliability of weak PUF. ISCAS 2017: 1-4 - [c156]Md. Nazmul Islam, Vinay C. Patil, Sandip Kundu:
Determining proximal geolocation of IoT edge devices via covert channel. ISQED 2017: 196-202 - [c155]Pavithra Ramesh, Vinay C. Patil, Sandip Kundu:
Peer pressure on identity: On requirements for disambiguating PUFs in noisy environment. NATW 2017: 1-4 - [c154]Md. Nazmul Islam, Sandip Kundu:
An analytical model for predicting the residual life of an IC and design of residual-life meter. VTS 2017: 1-6 - 2016
- [j55]Cristiana Bolchini, Sandip Kundu, Salvatore Pontarelli:
Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. IEEE Trans. Computers 65(3): 677-678 (2016) - [j54]Vikram B. Suresh, Sandip Kundu:
Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: A Case-Study on an SRAM Array. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 155-165 (2016) - [j53]Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, Sandip Kundu:
Abstraction-Guided Simulation Using Markov Analysis for Functional Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2): 285-297 (2016) - [j52]Sudarshan Srinivasan, Nithesh kurella, Israel Koren, Sandip Kundu:
Exploring Heterogeneity within a Core for Improved Power Efficiency. IEEE Trans. Parallel Distributed Syst. 27(4): 1057-1069 (2016) - [c153]Sandip Kundu:
Managing Reliability of Integrated Circuits: Lifetime Metering and Design for Healing. ATS 2016: 227 - [c152]Md. Nazmul Islam, Sandip Kundu:
Modeling Residual Lifetime of an IC Considering Spatial and Inter-Temporal Temperature Variations. ATS 2016: 240-245 - [c151]Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu:
On meta-obfuscation of physical layouts to conceal design characteristics. DFT 2016: 147-152 - [c150]Arunkumar Vijayakumar, Vinay C. Patil, Charles B. Prado, Sandip Kundu:
Machine learning resistant strong PUF: Possible or a pipe dream? HOST 2016: 19-24 - [c149]Sudarshan Srinivasan, Israel Koren, Sandip Kundu:
Improving performance per Watt of non-monotonic Multicore Processors via bottleneck-based online program phase classification. ICCD 2016: 528-535 - [c148]Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu:
Preventing integrated circuit piracy via custom encoding of hardware instruction set. ISQED 2016: 234-241 - [c147]Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu:
On testing physically unclonable functions for uniqueness. ISQED 2016: 368-373 - [c146]Md. Nazmul Islam, Sandip Kundu:
Modeling Residual Life of an IC Considering Multiple Aging Mechanisms. NATW 2016: 24-27 - [c145]Sandip Kundu, Omer Khan:
Efficient Error-Detection and Recovery Mechanisms for Reliability and Resiliency of Multicores. VLSID 2016: 12-13 - [c144]Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu:
An Efficient Method for Clock Skew Scheduling to Reduce Peak Current. VLSID 2016: 505-510 - [c143]Sudarshan Srinivasan, Nithesh kurella, Israel Koren, Sandip Kundu:
Dynamic Reconfiguration vs. DVFS: A Comparative Study on Power Efficiency of Processors. VLSID 2016: 563-564 - 2015
- [j51]Abhisek Pan, Rance Rodrigues, Sandip Kundu:
A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors. ACM Trans. Embed. Comput. Syst. 14(1): 12:1-12:26 (2015) - [j50]Rance Rodrigues, Israel Koren, Sandip Kundu:
Does the Sharing of Execution Units Improve Performance/Power of Multicores? ACM Trans. Embed. Comput. Syst. 14(1): 17:1-17:24 (2015) - [j49]Saraju P. Mohanty, Sandip Kundu:
Guest Editorial: Special Section on Circuit and System Design Methodologies for Emerging Technologies. IEEE Trans. Emerg. Top. Comput. 3(4): 456-457 (2015) - [c142]Arunkumar Vijayakumar, Sandip Kundu:
A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics. DATE 2015: 653-658 - [c141]Sudarshan Srinivasan, Israel Koren, Sandip Kundu:
Online mechanism for reliability and power-efficiency management of a dynamically reconfigurable core. ICCD 2015: 327-334 - 2014
- [j48]Rance Rodrigues, Arunachalam Annamalai, Sandip Kundu:
A low-power instruction replay mechanism for design of resilient microprocessors. ACM Trans. Embed. Comput. Syst. 13(4): 85:1-85:23 (2014) - [j47]Kunal P. Ganeshpure, Sandip Kundu:
Performance-driven dynamic thermal management of MPSoC based on task rescheduling. ACM Trans. Design Autom. Electr. Syst. 19(2): 11:1-11:33 (2014) - [j46]Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel:
Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2131-2144 (2014) - [c140]Sudarshan Srinivasan, Nithesh kurella, Israel Koren, Rance Rodrigues, Sandip Kundu:
A runtime support mechanism for fast mode switching of a self-morphing core for power efficiency. PACT 2014: 491-492 - [c139]Tiago A. O. Alves, Leandro A. J. Marzulo, Sandip Kundu, Felipe Maia Galvão França:
Domino effect protection on dataflow error detection and recovery. DFT 2014: 147-152 - [c138]Siva Nishok Dhanuskodi, Arunkumar Vijayakumar, Sandip Kundu:
A Chaotic Ring oscillator based Random Number Generator. HOST 2014: 160-165 - [c137]Tiago A. O. Alves, Sandip Kundu, Leandro A. J. Marzulo, Felipe Maia Galvão França:
Online error detection and recovery in dataflow execution. IOLTS 2014: 9-12 - [c136]Arunkumar Vijayakumar, Vinay C. Patil, Girish Paladugu, Sandip Kundu:
On pattern generation for maximizing IR drop. ISQED 2014: 731-737 - [c135]Arunachalam Annamalai, Rance Rodrigues, Israel Koren, Sandip Kundu:
Reducing Energy per Instruction via Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmetric Multicores. ISVLSI 2014: 436-441 - [c134]Bharath Phanibhushana, Sandip Kundu:
Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip. ISVLSI 2014: 486-491 - [c133]Arunkumar Vijayakumar, Sandip Kundu:
Glitch Power Reduction via Clock Skew Scheduling. ISVLSI 2014: 504-509 - [c132]Arunkumar Vijayakumar, Vinay C. Patil, Sandip Kundu:
On Maximizing Decoupling Capacitance of Clock-Gated Logic for Robust Power Delivery. ISVLSI 2014: 510-515 - [c131]Rance Rodrigues, Israel Koren, Sandip Kundu:
Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core. VLSID 2014: 204-209 - [c130]Raghavan Kumar, Siva Nishok Dhanuskodi, Sandip Kundu:
On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions. VLSID 2014: 381-386 - 2013
- [j45]Sandip Kundu, Saraju P. Mohanty, Nagarajan Ranganathan:
Guest editorial - Design methodologies for nanoelectronic digital and analogue circuits. IET Circuits Devices Syst. 7(5): 221-222 (2013) - [j44]Kunal P. Ganeshpure, Sandip Kundu:
Game theoretic approach for run-time task scheduling on an multi-processor system on chip. IET Circuits Devices Syst. 7(5): 243-252 (2013) - [j43]Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu:
A Study on the Use of Performance Counters to Estimate Power in Microprocessors. IEEE Trans. Circuits Syst. II Express Briefs 60-II(12): 882-886 (2013) - [j42]Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel:
A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 306-319 (2013) - [c129]Arunachalam Annamalai, Rance Rodrigues, Israel Koren, Sandip Kundu:
An opportunistic prediction-based thread scheduling to maximize throughput/watt in AMPs. PACT 2013: 63-72 - [c128]Rance Rodrigues, Sandip Kundu:
A low power architecture for online detection of execution errors in SMT processors. DFTS 2013: 33-38 - [c127]Vikram B. Suresh, Sandip Kundu:
Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM array. ICCD 2013: 201-206 - [c126]Sudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu:
On dynamic polymorphing of a superscalar core for improving energy efficiency. ICCD 2013: 495-498 - [c125]Arunachalam Annamalai, Raghavan Kumar, Arunkumar Vijayakumar, Sandip Kundu:
A system-level solution for managing spatial temperature gradients in thinned 3D ICs. ISQED 2013: 88-95 - [c124]Sudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu:
A study on polymorphing superscalar processor dynamically to improve power efficiency. ISVLSI 2013: 46-51 - [c123]Sudarshan Srinivasan, Raghavan Kumar, Sandip Kundu:
Program phase duration prediction and its application to fine-grain power management. ISVLSI 2013: 127-132 - [c122]Vikram B. Suresh, Sandip Kundu:
On analyzing and mitigating SRAM BER due to random thermal noise. ISVLSI 2013: 159-164 - [c121]Kunal P. Ganeshpure, Sandip Kundu:
On runtime task graph extraction in MPSoC. ISVLSI 2013: 171-176 - [c120]Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu:
Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis. VLSI Design 2013: 80-85 - 2012
- [j41]Michael Buttrick, Sandip Kundu:
On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs. J. Electron. Test. 28(1): 93-101 (2012) - [j40]Omer Khan, Sandip Kundu:
Empirical model for cooperative resizing of processor structures to exploit power-performance efficiency at runtime. IET Circuits Devices Syst. 6(5): 355-365 (2012) - [j39]Aswin Sreedhar, Sandip Kundu, Israel Koren:
On Reliability Trojan Injection and Detection. J. Low Power Electron. 8(5): 674-683 (2012) - [j38]Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu:
A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays. IEEE Trans. Computers 61(7): 986-998 (2012) - [j37]Sudarshan Srinivasan, Kunal P. Ganeshpure, Sandip Kundu:
A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1867-1880 (2012) - [j36]Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu:
Improving performance per watt of asymmetric multi-core processors via online program phase classification and adaptive core morphing. ACM Trans. Design Autom. Electr. Syst. 18(1): 5:1-5:23 (2012) - [j35]Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu:
Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 424-436 (2012) - [c119]Rance Rodrigues, Israel Koren, Sandip Kundu:
A mechanism to verify cache coherence transactions in multicore systems. DFT 2012: 211-216 - [c118]Arunachalam Annamalai, Rance Rodrigues, Israel Koren, Sandip Kundu:
Dynamic Thread Scheduling in Asymmetric Multicores to Maximize Performance-per-Watt. IPDPS Workshops 2012: 964-971 - [c117]Sudarshan Srinivasan, Sandip Kundu:
Functional test pattern generation for maximizing temperature in 3D IC chip stack. ISQED 2012: 109-116 - [c116]Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu:
On lithography aware metal-fill insertion. ISQED 2012: 200-207 - [c115]Nishant Dhumane, Sandip Kundu:
Critical area driven dummy fill insertion to improve manufacturing yield. ISQED 2012: 334-341 - [c114]Kunal P. Ganeshpure, Sandip Kundu:
Reducing Temperature Variation in 3D Integrated Circuits Using Heat Pipes. ISVLSI 2012: 45-50 - [c113]Kunal P. Ganeshpure, Sandip Kundu:
A DFT Methodology for Repairing Embedded Memories of Large MPSoCs. ISVLSI 2012: 108-113 - [c112]Arunkumar Vijayakumar, Raghavan Kumar, Sandip Kundu:
On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors. ISVLSI 2012: 120-125 - [c111]Raghavan Kumar, Vinay C. Patil, Sandip Kundu:
On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators. ISVLSI 2012: 165-170 - [c110]Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu:
Scalable Thread Scheduling in Asymmetric Multicores for Power Efficiency. SBAC-PAD 2012: 59-66 - 2011
- [j34]Omer Khan, Sandip Kundu:
Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors. IEEE Trans. Dependable Secur. Comput. 8(5): 714-727 (2011) - [j33]Omer Khan, Sandip Kundu:
Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors. Trans. High Perform. Embed. Archit. Compil. 4: 84-110 (2011) - [c109]Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu, Omer Khan:
Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores. PACT 2011: 121-130 - [c108]Rance Rodrigues, Israel Koren, Sandip Kundu:
An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors. PACT 2011: 219 - [c107]Rance Rodrigues, Sandip Kundu:
An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip Multiprocessors. Asian Test Symposium 2011: 161-166 - [c106]Michael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich:
Efficient BDD-based Fault Simulation in Presence of Unknown Values. Asian Test Symposium 2011: 383-388 - [c105]Aswin Sreedhar, Sandip Kundu:
On design of test structures for lithographic process corner identification. DATE 2011: 800-805 - [c104]Sandip Kundu, Aswin Sreedhar:
Modeling manufacturing process variation for design and test. DATE 2011: 1147-1152 - [c103]Michael Buttrick, Sandip Kundu:
On testing prebond dies with incomplete clock networks in a 3D IC using DLLs. DATE 2011: 1418-1423 - [c102]Aswin Sreedhar, Sandip Kundu:
Physically unclonable functions for embeded security based on lithographic variation. DATE 2011: 1632-1637 - [c101]Rance Rodrigues, Israel Koren, Sandip Kundu:
An Architecture to Enable Life Cycle Testing in CMPs. DFT 2011: 341-348 - [c100]Sudarshan Srinivasan, Bharath Phanibhushana, Arunkumar Vijayakumar, Sandip Kundu:
Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits. ACM Great Lakes Symposium on VLSI 2011: 265-270 - [c99]Raghavan Kumar, Harikrishnan Kumarapillai Chandrikakutty, Sandip Kundu:
On improving reliability of delay based Physically Unclonable Functions under temperature variations. HOST 2011: 142-147 - [c98]Bharath Phanibhushana, Kunal P. Ganeshpure, Sandip Kundu:
Task model for on-chip communication infrastructure design for multicore systems. ICCD 2011: 360-365 - [c97]Rance Rodrigues, Sandip Kundu:
On graceful degradation of microprocessors in presence of faults via resource banking. IOLTS 2011: 61-66 - [c96]Rance Rodrigues, Sandip Kundu:
On graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution units. IOLTS 2011: 67-72 - [c95]Aswin Sreedhar, Sandip Kundu:
On discovery of "missing" physical design rules via diagnosis of soft-faults. ISQED 2011: 251-256 - [c94]Rance Rodrigues, Sandip Kundu:
Model based double patterning lithography (DPL) and simulated annealing (SA). ISQED 2011: 376-383 - [c93]Sudarshan Srinivasan, Kunal P. Ganeshpure, Sandip Kundu:
Maximizing hotspot temperature: Wavelet based modelling of heating and cooling profile of functional workloads. ISQED 2011: 559-565 - [c92]Michael Buttrick, Sandip Kundu:
Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs. ISVLSI 2011: 194-199 - [c91]Nishant Dhumane, Sudheendra K. Srivathsa, Sandip Kundu:
Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability. ISVLSI 2011: 200-205 - [c90]Raghavan Kumar, Vinay C. Patil, Sandip Kundu:
Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain. ISVLSI 2011: 224-229 - [c89]Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu:
On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements. ISVLSI 2011: 248-253 - [c88]Priyamvada Vijayakumar, Vikram B. Suresh, Sandip Kundu:
Lithography aware critical area estimation and yield analysis. ITC 2011: 1-8 - 2010
- [j32]Alodeep Sanyal, Syed M. Alam, Sandip Kundu:
BIST to Detect and Characterize Transient and Parametric Failures. IEEE Des. Test Comput. 27(5): 50-59 (2010) - [j31]Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey:
Test pattern generation for droop faults. IET Comput. Digit. Tech. 4(4): 274-284 (2010) - [j30]Omer Khan, Sandip Kundu:
Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors. IEEE Trans. Computers 59(5): 651-665 (2010) - [j29]Alodeep Sanyal, Ashesh Rastogi, Wei Chen, Sandip Kundu:
An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects. IEEE Trans. Computers 59(7): 922-932 (2010) - [j28]Kunal P. Ganeshpure, Sandip Kundu:
On ATPG for Multiple Aggressor Crosstalk Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 774-787 (2010) - [j27]Hyunbean Yi, Sandip Kundu, Sangwook Cho, Sungju Park:
A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains. IEEE Trans. Circuits Syst. II Express Briefs 57-II(7): 561-565 (2010) - [j26]Hyunbean Yi, Sungju Park, Sandip Kundu:
On-Chip Support for NoC-Based SoC Debugging. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1608-1617 (2010) - [c87]Rance Rodrigues, Sandip Kundu:
A mask double patterning technique using litho simulation by wavelet transform. ACM Great Lakes Symposium on VLSI 2010: 103-106 - [c86]Omer Khan, Sandip Kundu:
A model to exploit power-performance efficiency in superscalar processors via structure resizing. ACM Great Lakes Symposium on VLSI 2010: 215-220 - [c85]Shruti Vyas, Aswin Sreedhar, Sandip Kundu:
TURBONFS: turbo nand flash search. ACM Great Lakes Symposium on VLSI 2010: 251-256 - [c84]Omer Khan, Sandip Kundu:
A self-adaptive scheduler for asymmetric multi-cores. ACM Great Lakes Symposium on VLSI 2010: 397-400 - [c83]Anup Das, Rance Rodrigues, Israel Koren, Sandip Kundu:
A study on performance benefits of core morphing in an asymmetric multicore processor. ICCD 2010: 17-22 - [c82]Rance Rodrigues, Sandip Kundu, Omer Khan:
Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor. ITC 2010: 219-228 - [c81]S. Saqib Khursheed, Shida Zhong, Robert C. Aitken, Bashir M. Al-Hashimi, Sandip Kundu:
Modeling the impact of process variation on resistive bridge defects. ITC 2010: 295-304 - [c80]Rance Rodrigues, Sandip Kundu:
Optical Lithography Simulation with Focus Variation using Wavelet Transform. VLSI Design 2010: 387-392
2000 – 2009
- 2009
- [j25]Rishad Ahmed Shafik, Bashir M. Al-Hashimi, Sandip Kundu, Alireza Ejlali:
Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip. J. Low Power Electron. 5(2): 145-156 (2009) - [j24]Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu:
An Improved Soft-Error Rate Measurement Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(4): 596-600 (2009) - [c79]Omer Khan, Sandip Kundu:
A self-adaptive system architecture to address transistor aging. DATE 2009: 81-86 - [c78]Kelageri Nagaraj, Sandip Kundu:
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation. DATE 2009: 292-295 - [c77]Aswin Sreedhar, Sandip Kundu:
On linewidth-based yield analysis for nanometer lithography. DATE 2009: 381-386 - [c76]Abhisek Pan, Omer Khan, Sandip Kundu:
Improving yield and reliability of chip multiprocessors. DATE 2009: 490-495 - [c75]Omer Khan, Sandip Kundu:
Hardware/software co-design architecture for thermal management of chip multiprocessors. DATE 2009: 952-957 - [c74]Kunal P. Ganeshpure, Ilia Polian, Sandip Kundu, Bernd Becker:
Reducing temperature variability by routing heat pipes. ACM Great Lakes Symposium on VLSI 2009: 63-68 - [c73]Aarti Choudhary, Sandip Kundu:
A process variation tolerant self-compensating FinFET based sense amplifier design. ACM Great Lakes Symposium on VLSI 2009: 161-164 - [c72]Kelageri Nagaraj, Sandip Kundu:
Process variation mitigation via post silicon clock tuning. ACM Great Lakes Symposium on VLSI 2009: 227-232 - [c71]Spandana Remarsu, Sandip Kundu:
On process variation tolerant low cost thermal sensor design in 32nm CMOS technology. ACM Great Lakes Symposium on VLSI 2009: 487-492 - [c70]Alodeep Sanyal, Abhisek Pan, Sandip Kundu:
A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits. ACM Great Lakes Symposium on VLSI 2009: 529-534 - [c69]Omer Khan, Sandip Kundu:
Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines. HiPEAC 2009: 293-307 - [c68]Aswin Sreedhar, Sandip Kundu:
Statistical timing analysis based on simulation of lithographic process. ICCD 2009: 29-34 - [c67]Rance Rodrigues, Aswin Sreedhar, Sandip Kundu:
Optical lithography simulation using wavelet transform. ICCD 2009: 427-432 - [c66]Alodeep Sanyal, Abhisek Pan, Sandip Kundu:
A study on impact of loading effect on capacitive crosstalk noise. ISQED 2009: 696-701 - [c65]Aarti Choudhary, Sandip Kundu:
A Process Variation Tolerant Self-Compensating Sense Amplifier Design. ISVLSI 2009: 263-267 - [c64]Kunal P. Ganeshpure, Sandip Kundu:
An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays. VLSI Design 2009: 233-238 - 2008
- [j23]Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu:
On Composite Leakage Current Maximization. J. Electron. Test. 24(4): 405-420 (2008) - [j22]Aswin Sreedhar, Sandip Kundu:
Lithography Simulation Basics and a Study on Impact of Lithographic Process Window on Gate and Path Delays. J. Low Power Electron. 4(3): 392-401 (2008) - [j21]Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker:
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 327-338 (2008) - [c63]Hyunbean Yi, Sungju Park, Sandip Kundu:
A Design-for-Debug (DfD) for NoC-Based SoC Debugging via NoC. ATS 2008: 289-294 - [c62]Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu:
On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits. DATE 2008: 616-621 - [c61]Sandip Kundu:
The Guiding Light for Chip Testing. DDECS 2008: 1 - [c60]Abhisek Pan, James W. Tschanz, Sandip Kundu:
A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit. DFT 2008: 343-351 - [c59]Hyunbean Yi, Sandip Kundu:
Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing. DFT 2008: 412-420 - [c58]Omer Khan, Sandip Kundu:
A framework for predictive dynamic temperature management of microprocessor systems. ICCAD 2008: 258-263 - [c57]Aswin Sreedhar, Sandip Kundu:
Modeling and analysis of non-rectangular transistors caused by lithographic distortions. ICCD 2008: 444-449 - [c56]Alodeep Sanyal, Syed M. Alam, Sandip Kundu:
A Built-In Self-Test Scheme for Soft Error Rate Characterization. IOLTS 2008: 65-70 - [c55]Alodeep Sanyal, Sandip Kundu:
A Built-in Test and Characterization Method for Circuit Marginality Related Failures. ISQED 2008: 838-843 - [c54]Kelageri Nagaraj, Sandip Kundu:
An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements. ITC 2008: 1-8 - [c53]Aswin Sreedhar, Sandip Kundu:
Statistical Yield Modeling for Sub-wavelength Lithography. ITC 2008: 1-8 - [c52]Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On Common-Mode Skewed-Load and Broadside Tests. VLSI Design 2008: 151-156 - 2007
- [j20]Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker:
Power Droop Testing. IEEE Des. Test Comput. 24(3): 276-284 (2007) - [j19]Dimitris Gizopoulos, Robert C. Aitken, Sandip Kundu:
Guest Editorial: Special Section on "Autonomous Silicon Validation and Testing of Microprocessors and Microprocessor-Based Systems". IEEE Trans. Very Large Scale Integr. Syst. 15(5): 493-494 (2007) - [c51]Ashesh Rastogi, Wei Chen, Sandip Kundu:
On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method. DAC 2007: 712-715 - [c50]Kunal P. Ganeshpure, Sandip Kundu:
Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults. DATE 2007: 540-545 - [c49]Aswin Sreedhar, Sandip Kundu:
On modeling impact of sub-wavelength lithography on transistors. ICCD 2007: 84-90 - [c48]Alodeep Sanyal, Sandip Kundu:
On Derating Soft Error Probability Based on Strength Filtering. IOLTS 2007: 152-160 - [c47]Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu:
Accelerating Soft Error Rate Testing Through Pattern Selection. IOLTS 2007: 191-193 - [c46]Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu:
A Study on Impact of Leakage Current on Dynamic Power. ISCAS 2007: 1069-1072 - [c45]Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu:
On Accelerating Soft-Error Detection by Targeted Pattern Generation. ISQED 2007: 723-728 - [c44]Kunal P. Ganeshpure, Sandip Kundu:
On ATPG for multiple aggressor crosstalk faults in presence of gate delays. ITC 2007: 1-7 - [c43]Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu:
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. VLSI Design 2007: 583-588 - 2006
- [j18]Sandip Kundu:
TTTC technical forum honoring Sudhakar M. Reddy. IEEE Des. Test Comput. 23(2): 167 (2006) - [c42]Sandip Kundu:
A design for failure analysis (DFFA) technique to ensure incorruptible signatures. DATE 2006: 309-310 - [c41]Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker:
Power Droop Testing. ICCD 2006: 243-250 - [c40]Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu:
A Pattern Generation Technique for Maximizing Power Supply Currents. ICCD 2006: 338-343 - [c39]Sandip Kundu, Ilia Polian:
An Improved Technique for Reducing False Alarms Due to Soft Errors. IOLTS 2006: 105-110 - [c38]Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu:
Test Pattern Generation for Power Supply Droop Faults. VLSI Design 2006: 343-348 - 2005
- [j17]Sandip Kundu, Sujit T. Zachariah, Yi-Shing Chang, Chandra Tirumurti:
On modeling crosstalk faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1909-1915 (2005) - [c37]Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker:
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. Asian Test Symposium 2005: 266-271 - [c36]Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
Path-oriented transition fault test generation considering operating conditions. ETS 2005: 54-59 - [c35]Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker:
Transient fault characterization in dynamic noisy environments. ITC 2005: 10 - [c34]Ilia Polian, Sandip Kundu, Jean-Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker:
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS 2005: 343-348 - 2004
- [j16]Rob Aitken, Stefan Eichenberger, Gary Maier, Sandip Kundu, Hank Walker:
ITC 2003 Roundtable: Design for Manufacturability. IEEE Des. Test Comput. 21(2): 144-156 (2004) - [j15]Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy:
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. IEEE Trans. Computers 53(1): 83-88 (2004) - [j14]Sandip Kundu:
Pitfalls of hierarchical fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(2): 312-314 (2004) - [j13]Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On the characterization and efficient computation of hard-to-detect bridging faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1640-1649 (2004) - [c33]Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang:
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. DATE 2004: 1078-1083 - [c32]Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu:
Static statistical timing analysis for latch-based pipeline designs. ICCAD 2004: 468-472 - [c31]Sandip Kundu, T. M. Mak, Rajesh Galivanche:
Trends in manufacturing test methods and their implications. ITC 2004: 679-687 - 2003
- [c30]Bill Grundmann, Rajesh Galivanche, Sandip Kundu:
Circuit and Platform Design Challenges in Technologies beyond 90nm. DATE 2003: 10044-10049 - [c29]Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti:
On Modeling Cross-Talk Faults. DATE 2003: 10490-10495 - [c28]Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On the Characterization of Hard-to-Detect Bridging Faults. DATE 2003: 11012-11019 - [c27]Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On path selection for delay fault testing considering operating conditions [logic IC testing]. ETW 2003: 141-146 - [c26]Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. ITC 2003: 1060-1068 - 2002
- [c25]Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy:
On output response compression in the presence of unknown output values. DAC 2002: 255-258 - 2001
- [j12]Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche:
Test Challenges in Nanometer Technologies. J. Electron. Test. 17(3-4): 209-218 (2001) - [c24]Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic:
Fast Statistical Timing Analysis By Probabilistic Event Propagation. DAC 2001: 661-666 - [c23]Sitaram Yadavalli, Sandip Kundu:
On Fault-Simulation Through Embedded Memories On Large Industrial Designs. VLSI Design 2001: 117-121 - 2000
- [c22]Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu:
Performance sensitivity analysis using statistical method and its applications to delay. ASP-DAC 2000: 587-592 - [c21]Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche:
Test challenges in nanometer technologies. ETW 2000: 83-90
1990 – 1999
- 1999
- [c20]Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu:
On Detecting Bridges Causing Timing Failures. ICCD 1999: 400-406 - 1998
- [c19]Anirudh Devgan, Sandip Kundu:
Timing Analysis and Optimization: From Devices to Systems (Abstract of Embedded Tutorial). ASP-DAC 1998: 345 - [c18]Sandip Kundu:
IDDQ Defect Detection in Deep Submicron CMOS ICs. Asian Test Symposium 1998: 150-152 - [c17]Sandip Kundu:
GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification. ITC 1998: 372-381 - 1997
- [c16]Sandip Kundu, Uttam Ghoshal:
Inductance analysis of on-chip interconnects [deep submicron CMOS]. ED&TC 1997: 252-255 - [c15]Anirudh Devgan, Leon Stok, Sandip Kundu:
Timing analysis and optimization: from devices to systems (tutorial). ICCAD 1997 - 1996
- [j11]Sandip Kundu, Egor S. Sogomonyan, Michael Gössel, Steffen Tarnick:
Self-Checking Comparator with One Periodic Output. IEEE Trans. Computers 45(3): 379-380 (1996) - 1995
- [j10]Sandip Kundu:
On Construction of Non-systematic t-Symmetric Error Correcting/All Unidirectional Error Detecting Codes. IEICE Trans. Inf. Syst. 78-D(5): 596-599 (1995) - [c14]Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, Parimal Pal Chaudhuri:
Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium 1995: 189-190 - 1994
- [j9]Sandip Kundu:
An incremental algorithm for identification of longest (shortest) paths. Integr. 17(1): 25-31 (1994) - [j8]Sandip Kundu:
An efficient technique for obtaining unate implementation of functions through input encoding. Integr. 17(3): 265-270 (1994) - [j7]Leendert M. Huisman, Sandip Kundu:
Highly Reliable Symmetric Networks. IEEE Trans. Parallel Distributed Syst. 5(1): 94-97 (1994) - [j6]Sandip Kundu:
Diagnosing scan chain faults. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 512-516 (1994) - [c13]Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther:
Microprocessor Testing: Which Technique is Best? (Panel). DAC 1994: 294 - [c12]Daniel Brand, Anthony D. Drumm, Sandip Kundu, Prakash Narain:
Incremental synthesis. ICCAD 1994: 14-18 - [c11]Sandip Kundu:
Multifault Testable Circuits Based on Binary Parity Diagrams. ICCD 1994: 363-366 - 1993
- [c10]Ankan K. Pramanick, Sandip Kundu:
Design of Scan-Based Path-Delay-Testable Sequential Circuits. ITC 1993: 962-971 - [c9]Sandip Kundu, Ankan K. Pramanick:
Testability preserving Boolean transforms for logic synthesis. VTS 1993: 131-138 - [c8]Sandip Kundu:
On diagnosis of faults in a scan-chain. VTS 1993: 303-308 - 1992
- [c7]Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy:
A Small Test Generator for Large Designs. ITC 1992: 30-40 - 1991
- [j5]Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha:
Design of robustly testable combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 1036-1048 (1991) - [c6]Roy Thomas, Sandip Kundu:
Synthesis of fully testable sequential machines. EURO-DAC 1991: 283-288 - [c5]Sandip Kundu, Indira Nair, Leendert M. Huisman, Vijay S. Iyengar:
Symbolic implication in test generation. EURO-DAC 1991: 492-496 - 1990
- [j4]Sandip Kundu, Sudhakar M. Reddy:
Embedded Totally Self-Checking Checkers: A Practical Design. IEEE Des. Test Comput. 7(4): 5-12 (1990) - [j3]Sandip Kundu, Sudhakar M. Reddy:
Robust tests for parity trees. J. Electron. Test. 1(3): 191-200 (1990) - [j2]Sandip Kundu, Sudhakar M. Reddy:
On Symmetric Error Correcting and All Unidirectional Error Detecting Codes. IEEE Trans. Computers 39(6): 752-761 (1990)
1980 – 1989
- 1989
- [j1]Sandip Kundu:
Design of multioutput CMOS combinational logic circuits for robust testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(11): 1222-1226 (1989) - [c4]Sandip Kundu, Sudhakar M. Reddy:
Design of TSC checkers for implementation in CMOS technology. ICCD 1989: 116-119 - 1988
- [c3]Sandip Kundu, Sudhakar M. Reddy:
On the design of robust testable CMOS combinational logic circuits. FTCS 1988: 220-225 - [c2]Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha:
On the design of robust multiple fault testable CMOS combinational logic circuits. ICCAD 1988: 240-243 - [c1]Sandip Kundu, Sudhakar M. Reddy:
Robust Tests for Parity Trees. ITC 1988: 680-687
Coauthor Index
Felipe M. G. França
aka: Felipe Maia Galvão França
aka: Felipe Maia Galvão França
Leandro A. J. Marzulo
aka: Leandro Augusto Justen Marzulo
aka: Leandro Augusto Justen Marzulo
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