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2020 – today
- 2020
[c18]Chih-Jen Hsu, Chi-An Wu, Ching-Yi Huang, Kei-Yong Khoo:
ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk. ICCAD 2020: 68:1-68:4
2010 – 2019
- 2019
- [c17]Ching-Yi Huang, Chi-An (Rocky) Wu, Tung-Yuan Lee, Chih-Jen (Jacky) Hsu, Kei-Yong Khoo:
2019 CAD Contest: Logic Regression on High Dimensional Boolean Space. ICCAD 2019: 1-6 - 2018
- [c16]Yung-Chih Chen, Wei-An Ji, Chih-Chung Wang, Ching-Yi Huang, Chia-Cheng Wu, Chia-Chun Lin, Chun-Yao Wang:
Using range-equivalent circuits for facilitating bounded sequential equivalence checking. VLSI-DAT 2018: 1-4 - 2017
- [j8]Yun-Jui Li, Ching-Yi Huang, Chia-Cheng Wu
, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan:
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1477-1489 (2017) - [c15]Ching-Yi Huang, Chih-Jen Hsu, Chi-An Wu, Kei-Yong Khoo:
ICCAD-2017 CAD contest in resource-aware patch generation. ICCAD 2017: 857-862 - 2016
- [j7]Tai-Lin Chen, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen:
An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm. J. Multiple Valued Log. Soft Comput. 27(1): 1-19 (2016) - [j6]Chen-Yu Lin, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Chiou-Ting Hsu:
Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks. IEEE Trans. Multi Scale Comput. Syst. 2(4): 225-233 (2016) - [j5]Ching-Hsuan Ho, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang, Suman Datta, Vijaykrishnan Narayanan:
Area-Aware Decomposition for Single-Electron Transistor Arrays. ACM Trans. Design Autom. Electr. Syst. 21(4): 70:1-70:20 (2016) - [j4]Ching-Yi Huang, Yun-Jui Li, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays. IEEE Trans. Very Large Scale Integr. Syst. 24(6): 2321-2334 (2016) - [c14]Yu-Min Chou, Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang:
MajorSat: A SAT solver to majority logic. ASP-DAC 2016: 480-485 - 2015
- [j3]Ching-Yi Huang, Zheng-Shan Yu, Yung-Chun Hu, Tung-Chen Tsou, Chun-Yao Wang, Yung-Chih Chen:
Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 615-628 (2015) - [j2]Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Yung-Chih Chen, Chun-Yao Wang, Suman Datta, Vijaykrishnan Narayanan:
Synthesis for Width Minimization in the Single-Electron Transistor Array. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2862-2875 (2015) - [c13]Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays. ASP-DAC 2015: 118-123 - [c12]Wan-Chen Weng, Yung-Chih Chen, Jui-Hung Chen, Ching-Yi Huang, Chun-Yao Wang:
Using structural relations for checking combinationality of cyclic circuits. DATE 2015: 325-328 - [c11]Jui-Hung Chen, Yung-Chih Chen, Wan-Chen Weng, Ching-Yi Huang, Chun-Yao Wang:
Synthesis and verification of cyclic combinational circuits. SoCC 2015: 257-262 - 2014
- [c10]Chia-Chun Lin, Chun-Yao Wang, Yung-Chih Chen, Ching-Yi Huang:
Rewiring for threshold logic circuit minimization. DATE 2014: 1-6 - [c9]Chian-Wei Liu, Chang-En Chiang, Ching-Yi Huang, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
Width minimization in the Single-Electron Transistor array synthesis. DATE 2014: 1-4 - 2013
- [j1]Yung-Chih Chen, Chun-Yao Wang, Ching-Yi Huang:
Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(10): 1473-1483 (2013) - [c8]Chang-En Chiang, Li-Fu Tang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan:
On reconfigurable single-electron transistor arrays synthesis using reordering techniques. DATE 2013: 1807-1812 - [c7]Chen-Kuan Tsai, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen:
Sensitization criterion for threshold logic circuits and its application. ICCAD 2013: 226-233 - [c6]Yen-Chi Yang, Chun-Yao Wang, Ching-Yi Huang, Yung-Chih Chen:
Pattern generation for Mutation Analysis using Genetic Algorithms. ISCAS 2013: 2545-2548 - 2012
- [c5]Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen:
A probabilistic analysis method for functional qualification under Mutation Analysis. DATE 2012: 147-152 - [c4]Ching-Yi Huang, Chi-Wen Huang, Chia-Jung Wu, Gwo-Dong Chen, Kuang-Hung Chiang:
Using "Learning Video Portfolio" to Enhance Students' Metacognition in Authentic Learning. ICALT 2012: 613-617 - [c3]Ching-Yi Huang, Daw-Ming Lee, Chun-Chi Lin, Chun-Yao Wang:
Error Injection & Correction: An efficient formal logic restructuring algorithm. ISOCC 2012: 188-191 - 2011
- [c2]Pin-Yi Kuo, Chun-Yao Wang, Ching-Yi Huang:
On rewiring and simplification for canonicity in threshold logic circuits. ICCAD 2011: 396-403 - [c1]Yen-An Chen, Chun-Yao Wang, Ching-Yi Huang, Hsiu-Yi Lin:
A register-transfer level testability analyzer. SoCC 2011: 219-224
Coauthor Index
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