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ORCIDRenato P. Ribas
Renato Perez Ribas
Person information
- affiliation: Federal University of Rio Grande do Sul, Porto Alegre, Brazil
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2020 – today
- 2024
[c80]Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas:
Extending Multilevel ALS to Design ATMRs. LASCAS 2024: 1-5- 2023
- [c79]Gabriel Ammes, Paulo F. Butzen
, André Inácio Reis, Renato P. Ribas:
Evaluation of Digital Circuit Design by Combining Two - and Multi-Level Approximate Logic Synthesis. ISVLSI 2023: 1-6 - [c78]Gabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas:
ATMR design by construction based on two-level ALS. SBCCI 2023: 1-6 - [c77]Marco Antônio Athayde de Aguiar Vieira, Anderson Rocha Tavares, Renato Perez Ribas:
Hybrid Minimax-MCTS and Difficulty Adjustment for General Game Playing. SBGames 2023: 20-27 - [i2]Marco Antônio Athayde de Aguiar Vieira, Anderson Rocha Tavares, Renato Perez Ribas:
Hybrid Minimax-MCTS and Difficulty Adjustment for General Game Playing. CoRR abs/2310.16581 (2023) - 2022
- [j22]Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas:
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5126-5130 (2022) - 2021
- [i1]Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas:
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. CoRR abs/2112.00621 (2021) - 2020
- [j21]Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas:
Exact Benchmark Circuits for Logic Synthesis. IEEE Des. Test 37(3): 51-58 (2020) - [j20]Augusto Neutzling, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas:
maj-n Logic Synthesis for Emerging Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 747-751 (2020) - [j19]Vinicius N. Possani, Alan Mishchenko, Renato P. Ribas, André Inácio Reis:
Parallel Combinational Equivalence Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3081-3092 (2020)
2010 – 2019
- 2019
- [j18]Augusto Neutzling, Jody Maick Matos, Alan Mishchenko, André Inácio Reis, Renato P. Ribas:
Effective Logic Synthesis for Threshold Logic Circuit Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 926-937 (2019) - [j17]Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
Four-Level Forms for Memristive Material Implication Logic. IEEE Trans. Very Large Scale Integr. Syst. 27(5): 1228-1232 (2019) - 2018
- [j16]Augusto Neutzling, Mayler G. A. Martins, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
A Simple and Effective Heuristic Method for Threshold Logic Identification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(5): 1023-1036 (2018) - [c76]Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis:
Unlocking fine-grain parallelism for AIG rewriting. ICCAD 2018: 87 - [c75]Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, André Inácio Reis, Renato P. Ribas:
Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation. SBCCI 2018: 1-6 - 2017
- [j15]Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.:
Transistor Count Optimization in IG FinFET Network Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1483-1496 (2017) - [j14]Vinícius Dal Bem, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC. IEEE Trans. Emerg. Top. Comput. 5(2): 247-259 (2017) - [c74]Jeferson José Baqueta, Felipe S. Marranghello, Vinicius N. Possani, Augusto Neutzling, André Inácio Reis, Renato P. Ribas:
Binary adder circuit design using emerging MIGFET devices. ISQED 2017: 125-130 - 2016
- [j13]Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Graph-Based Transistor Network Generation Method for Supergate Design. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 692-705 (2016) - [c73]Andres M. A. Valdes, Vinicius N. Possani, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Performance evaluation of optimized transistor networks built using independent-gate FinFET. LASCAS 2016: 227-230 - [c72]M. De Carvalho, Maurício Altieri, L. Puricelli, Renato P. Butzen, Renato P. Ribas, Eric E. Fabris:
On-silicon validation of a benchmark generation methodology for effectively evaluating combinational cell library design. LATS 2016: 135-140 - 2015
- [j12]Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas:
Factored Forms for Memristive Material Implication Stateful Logic. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 267-278 (2015) - [c71]Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis:
Enhanced Spin-Diode Synthesis Using Logic Sharing. DSD 2015: 218-224 - [c70]Augusto Neutzling, Jody Maick Matos, André Inácio Reis, Renato P. Ribas, Alan Mishchenko:
Threshold Logic Synthesis Based on Cut Pruning. ICCAD 2015: 494-499 - [c69]Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
SOP based logic synthesis for memristive IMPLY stateful logic. ICCD 2015: 228-235 - [c68]Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. ICCD 2015: 680-687 - [c67]Helder H. Avelar, Paulo F. Butzen, Renato P. Ribas:
Automatic circuit generation for sequential logic debug. ICECS 2015: 141-144 - [c66]Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Fast buffer delay estimation considering time-dependent dielectric breakdown. ISCAS 2015: 177-180 - [c65]Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas:
Improved logic synthesis for memristive stateful logic using multi-memristor implication. ISCAS 2015: 181-184 - [c64]Mayler G. A. Martins, Jody Maick Matos, Renato P. Ribas, André Inácio Reis, Guilherme Schlinker, Lucio Rech, Jens Michelsen:
Open Cell Library in 15nm FreePDK Technology. ISPD 2015: 171-178 - [c63]Jody Maick Matos, Augusto Neutzling, Renato P. Ribas, André Inácio Reis:
A Benchmark Suite to Jointly Consider Logic Synthesis and Physical Design. ISPD 2015: 185-192 - [c62]Bruno Canal, Cicero S. Nunes, Renato P. Ribas, Eric E. Fabris:
MCML Gate Design for Standard Cell Library. SBCCI 2015: 3:1-3:6 - 2014
- [c61]Matheus T. Moreira, Augusto Neutzling, Mayler G. A. Martins, André Inácio Reis, Renato P. Ribas, Ney Calazans:
Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? ASYNC 2014: 53-60 - [c60]Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
A constructive approach for threshold logic circuit synthesis. ISCAS 2014: 385-388 - [c59]Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
CMOS inverter analytical delay model considering all operating regions. ISCAS 2014: 1452-1455 - [c58]Iuri A. C. Gomes, Mayler G. A. Martins, Fernanda Lima Kastensmidt, André Inácio Reis, Renato P. Ribas, Sylvain P. Novales:
Methodology for achieving best trade-off of area and fault masking coverage in ATMR. LATW 2014: 1-6 - [c57]Jody Maick Matos, Marcus Ritt, Renato P. Ribas, André Inácio Reis:
Deriving Reduced Transistor Count Circuits from AIGs. SBCCI 2014: 40:1-40:7 - [c56]Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Jr.:
Exploring Independent Gates in FinFET-Based Transistor Network Generation. SBCCI 2014: 41:1-41:6 - 2013
- [j11]Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas:
BTI, HCI and TDDB aging impact in flip-flops. Microelectron. Reliab. 53(9-11): 1355-1359 (2013) - [j10]Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
BTI and HCI first-order aging estimation for early use in standard cell technology mapping. Microelectron. Reliab. 53(9-11): 1360-1364 (2013) - [c55]Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Efficient transistor-level design of CMOS gates. ACM Great Lakes Symposium on VLSI 2013: 191-196 - [c54]Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
CMOS inverter delay model based on DC transfer curve for slow input. ISQED 2013: 651-657 - [c53]Lucas Machado, Vinícius Dal Bem, Francesc Moll, Sergio Gómez, Renato P. Ribas, André Inácio Reis:
Logic synthesis for manufacturability considering regularity and lithography printability. ISVLSI 2013: 230-235 - [c52]Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
Iterative remapping respecting timing constraints. ISVLSI 2013: 236-241 - [c51]Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
Transistor-level optimization of CMOS complex gates. LASCAS 2013: 1-4 - [c50]Caio G. P. Alegretti, Vinícius Dal Bem, Renato P. Ribas, André Inácio Reis:
Analytical logical effort formulation for minimum active area under delay constraints. SBCCI 2013: 1-6 - [c49]Vinicius Callegaro, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Read-polarity-once Boolean functions. SBCCI 2013: 1-6 - [c48]Kim A. Escobar, Renato P. Ribas:
Parallel prefix adder design using quantum-dot cellular automata. SBCCI 2013: 1-6 - [c47]Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Delay model for static CMOS complex gates. SBCCI 2013: 1-6 - [c46]Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis:
Spin diode network synthesis using functional composition. SBCCI 2013: 1-6 - [c45]Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Synthesis of threshold logic gates to nanoelectronics. SBCCI 2013: 1-6 - [c44]Cicero Nunes, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas:
A methodology to evaluate the aging impact on flip-flops performance. SBCCI 2013: 1-6 - [c43]Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.:
Improving the methodology to build non-series-parallel transistor arrangements. SBCCI 2013: 1-6 - [c42]Alberto Wiltgen, Kim A. Escobar, André Inácio Reis, Renato P. Ribas:
Power consumption analysis in static CMOS gates. SBCCI 2013: 1-6 - 2012
- [j9]Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
Design of CMOS logic gates with enhanced robustness against aging degradation. Microelectron. Reliab. 52(9-10): 1822-1826 (2012) - [c41]Mayler G. A. Martins, Renato P. Ribas, André Inácio Reis:
Functional composition: A new paradigm for performing logic synthesis. ISQED 2012: 236-242 - [c40]Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
Lithography analysis of via-configurable transistor-array fabrics. NORCHIP 2012: 1-4 - [c39]Lucas Machado, Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
KL-cut based digital circuit remapping. NORCHIP 2012: 1-4 - [c38]Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Design-oriented delay model for CMOS inverter. SBCCI 2012: 1-6 - [c37]Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. SBCCI 2012: 1-6 - 2011
- [j8]Renato P. Ribas, Simone Bavaresco, N. Schuch, Vinicius Callegaro, Marcelo Lubaszewski, André Inácio Reis:
Contributions to the evaluation of ensembles of combinational logic gates. Microelectron. J. 42(2): 371-381 (2011) - [c36]Martin Elhøj, André Inácio Reis, Renato P. Ribas, Fabrizio Ferrandi, Christian Pilato, Francesc Moll, Miguel Miranda, Petr Dobrovolný, Nigel Woolaway, Arnaud Grasset, Philippe Bonnot, Giuseppe Desoli, Davide Pandini:
SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels. ARCS Workshops 2011 - [c35]Thiago Figueiro, Renato P. Ribas, André Inácio Reis:
Constructive AIG optimization through functional composition. ARCS Workshops 2011 - [c34]Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas, Francesc Moll:
Transistor Sizing Analysis of Regular Fabrics. ARCS Workshops 2011 - [c33]Mayler G. A. Martins, Vinicius Callegaro, Renato P. Ribas, André Inácio Reis:
Efficient method to compute minimum decision chains of Boolean functions. ACM Great Lakes Symposium on VLSI 2011: 419-422 - [c32]Vinícius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, André Inácio Reis, Renato P. Ribas:
Impact and optimization of lithography-aware regular layout in digital circuit design. ICCD 2011: 279-284 - [c31]Renato P. Ribas, André Inácio Reis, André Ivanov:
Performance and functional test of flip-flops using ring oscillator structure. IDT 2011: 42-47 - [c30]Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov:
Self-checking test circuits for latches and flip-flops. IOLTS 2011: 210-213 - [c29]Thiago Figueiro, Renato P. Ribas, André Inácio Reis:
Constructive AIG optimization considering input weights. ISQED 2011: 769-776 - [c28]Renato P. Ribas, Yuyang Sun, André Inácio Reis, André Ivanov:
Ring oscillators for functional and delay test of latches and flip-flops. SBCCI 2011: 67-72 - [c27]Felipe S. Marranghello, Vinícius Dal Bem, André Inácio Reis, Francesc Moll, Renato P. Ribas:
Transistor sizing in lithography-aware regular fabrics. SBCCI 2011: 97-102 - [c26]Vinícius Dal Bem, Paulo F. Butzen, Carlos Eduardo Klock, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
Area impact analysis of via-configurable regular fabric for digital integrated circuit design. SBCCI 2011: 103-108 - 2010
- [j7]Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance for Nanoscaled CMOS Circuits. J. Low Power Electron. 6(1): 192-200 (2010) - [j6]Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, André Inácio Reis, Renato P. Ribas:
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits. Microelectron. J. 41(4): 247-255 (2010) - [j5]Digeorgia N. da Silva, André Inácio Reis, Renato P. Ribas:
Gate delay variability estimation method for parametric yield improvement in nanometer CMOS technology. Microelectron. Reliab. 50(9-11): 1223-1229 (2010) - [j4]Paulo F. Butzen, Vinícius Dal Bem, André Inácio Reis, Renato P. Ribas:
Transistor network restructuring against NBTI degradation. Microelectron. Reliab. 50(9-11): 1298-1303 (2010) - [j3]Carlos Eduardo Klock, Renato Perez Ribas, André Inácio Reis:
Karma: um ambiente para o aprendizado de síntese de funções Booleanas. Revista Brasileira de Informática na Educ. 18(2): 33-42 (2010) - [c25]Osvaldo Martinello, Felipe S. Marques, Renato P. Ribas, André Inácio Reis:
KL-Cuts: A new approach for logic synthesis targeting multiple output blocks. DATE 2010: 777-782 - [c24]Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, André Inácio Reis:
Boolean factoring with multi-objective goals. ICCD 2010: 229-234 - [c23]Vinicius Callegaro, Felipe de Souza Marques, Carlos Eduardo Klock, Leomar Soares da Rosa Jr., Renato P. Ribas, André Inácio Reis:
SwitchCraft: a framework for transistor network design. SBCCI 2010: 49-53 - [c22]Felipe S. Marques, Osvaldo Martinello, Renato P. Ribas, André Inácio Reis:
Improvements on the detection of false paths by using unateness and satisfiability. SBCCI 2010: 192-197
2000 – 2009
- 2009
- [j2]Digeorgia N. da Silva, André Inácio Reis, Renato P. Ribas:
CMOS logic gate performance variability related to transistor network arrangements. Microelectron. Reliab. 49(9-11): 977-981 (2009) - [c21]Renato P. Ribas, Simone Bavaresco, Marcelo Lubaszewski, André Inácio Reis:
Efficient Test Circuit to Qualify Logic Cells. ISCAS 2009: 2733-2736 - [c20]Leomar S. da Rosa Jr., Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis:
Switch level optimization of digital CMOS gate networks. ISQED 2009: 324-329 - [c19]Paulo F. Butzen, André Inácio Reis, Renato P. Ribas:
Routing Resistance Influence in Loading Effect on Leakage Analysis. PATMOS 2009: 317-325 - [e1]Ivan Saraiva Silva, Renato P. Ribas, Calvin Plett:
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009. ACM 2009, ISBN 978-1-60558-705-9 [contents] - 2008
- [c18]Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas:
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. ACM Great Lakes Symposium on VLSI 2008: 407-410 - [c17]Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis:
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. ISQED 2008: 47-52 - 2007
- [c16]Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas:
Modeling and estimating leakage current in series-parallel CMOS networks. ACM Great Lakes Symposium on VLSI 2007: 269-274 - [c15]Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
DAG based library-free technology mapping. ACM Great Lakes Symposium on VLSI 2007: 293-298 - [c14]Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas:
Modeling Subthreshold Leakage Current in General Transistor Networks. ISVLSI 2007: 512-513 - [c13]Carlos Eduardo Klock, Felipe Ribeiro Schneider, M. V. N. Gomes, Dionatan S. Moura, Renato P. Ribas, André Inácio Reis:
KARMA: A Didactic Tool for Two-Level Logic Synthesis. MSE 2007: 59-60 - [c12]Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas:
Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates. PATMOS 2007: 474-484 - [c11]Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider:
A comparative study of CMOS gates with minimum transistor stacks. SBCCI 2007: 93-98 - 2006
- [c10]R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis:
Asynchronous circuit design on reconfigurable devices. SBCCI 2006: 20-25 - [c9]Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
Fast disjoint transistor networks from BDDs. SBCCI 2006: 137-142 - 2005
- [c8]Felipe S. Marques, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
A new approach to the use of satisfiability in false path detection. ACM Great Lakes Symposium on VLSI 2005: 308-311 - [c7]João Daniel Togni, Renato P. Ribas, Maria Lúcia Blanck Lisbôa, André Inácio Reis:
Tool integration using the web-services approach. ACM Great Lakes Symposium on VLSI 2005: 337-340 - [c6]Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
Exact lower bound for the number of switches in series to implement a combinational logic cell. ICCD 2005: 357-362 - 2004
- [c5]Mário C. B. Osorio, Carlos A. Sampaio, André Inácio Reis, Renato P. Ribas:
Enhanced 32-bit carry lookahead adder using multiple output enable-disable CMOS differential logic. SBCCI 2004: 181-185 - 2003
- [c4]Renato E. B. Poli, Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis:
Unified Theory to Build Cell-Level Transistor Networks from BDDs. SBCCI 2003: 199-204 - 2002
- [c3]Felipe Ribeiro Schneider, Vinícius P. Correia, Renato P. Ribas, André Inácio Reis:
Comparing Transistor-Level Implementations of 4-Input Logic Functions. IWLS 2002: 361-365 - [c2]João Daniel Togni, Felipe Ribeiro Schneider, Vinícius P. Correia, Renato P. Ribas, André Inácio Reis:
Automatic Generation of Digital Cell Libraries. SBCCI 2002: 265-270 - 2001
- [j1]Renato P. Ribas, André Inácio Reis, Marcelo Lubaszewski:
Concepção de Circuitos e Sistemas Integrados. RITA 8(1): 7-21 (2001) - [c1]Renato P. Ribas, F. Rudge Barbosa, N. Turatti:
Integrated Circuits Design Teaching Using Professional CAD Environments. MSE 2001: 77-
Coauthor Index
Felipe S. Marques 0001
aka: Felipe de Souza Marques
aka: Felipe de Souza Marques
Vinicius N. Possani
aka: Vinicius Neves Possani
aka: Vinicius Neves Possani
[c80] [c79] [c78] [j21] [j20] [j19] [j18] [j17] [j16] [c76] [c75] [j15] [j14] [c74] [j13] [c73] [j12] [c71] [c70] [c69] [c68] [c66] [c65] [c64] [c63] [c61] [c60] [c59] [c58] [c57] [c56] [j11] [j10] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c47] [c46] [c45] [c44] [c43] [c42] [j9] [c41] [c40] [c39] [c38] [c37] [j8] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [j7] [j6] [j5] [j4] [j3] [c25] [c24] [c23] [c22] [j2] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [j1]
Leomar S. da Rosa Jr.
aka: Leomar Soares da Rosa Jr.
aka: Leomar Soares da Rosa Jr.
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