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2010 – 2019
- 2017
[j7]Shuli Gao, Dhamin Al-Khalili
, J. M. Pierre Langlois, Noureddine Chabini:
Efficient Realization of BCD Multipliers Using FPGAs. Int. J. Reconfigurable Comput. 2017: 2410408:1-2410408:12 (2017)- [c10]Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini:
Decimal floating-point multiplier with binary-decimal compression based fixed-point multiplier. CCECE 2017: 1-6 - [c9]Shuli Gao, Jian Zhang, Jian Song, Hui Yang, Xi Chu:
Random channel generator of the integrated power line communication and visible light communication. ISPLC 2017: 1-7 - 2016
- [j6]Shuli Gao, Yanli Guo, Jianbin Chen, Lin Li:
Factors affecting the performance of knowledge collaboration in virtual team based on capital appreciation. Inf. Technol. Manag. 17(2): 119-131 (2016) - 2014
- [c8]Shuli Gao, Sidney N. Givigi, Alain J. G. Beaulieu:
FPGA implementation of multiple Pursuit-Evasion games with decentralized Learning Automata. SysCon 2014: 78-82 - 2012
- [j5]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois:
Asymmetric large size multipliers with optimised FPGA resource utilisation. IET Comput. Digit. Tech. 6(6): 372-383 (2012) - [c7]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
An improved BCD adder using 6-LUT FPGAs. NEWCAS 2012: 13-16 - 2011
- [j4]Hui Xu, Shuli Gao, Quanwen Liu, Dun Pan, Lihua Wang, Shuzhen Ren, Min Ding, Jingwen Chen, Gang Liu:
A Highly Sensitive and Selective Competition Assay for the Detection of Cysteine Using Mercury-Specific DNA, Hg2+ and Sybr Green I. Sensors 11(11): 10187-10196 (2011) - [c6]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Asymmetric large size multiplication using embedded blocks with efficient compression technique in FPGAs. ICECS 2011: 137-140 - [c5]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Asymmetric Large Size Signed Multipliers Using Embedded Blocks in FPGAs. IPDPS Workshops 2011: 271-277 - 2010
- [j3]Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
FPGA-Based Efficient Design Approaches for Large Size Two's Complement Squarers. J. Signal Process. Syst. 58(1): 3-15 (2010)
2000 – 2009
- 2009
- [j2]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs. Int. J. Reconfigurable Comput. 2009: 145130:1-145130:11 (2009) - [c4]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini:
Two level decomposition based matrix multiplication for FPGAs. ICECS 2009: 427-430 - 2007
- [j1]Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
Optimised realisations of large integer multipliers and squarers using embedded blocks. IET Comput. Digit. Tech. 1(1): 9-16 (2007) - [c3]Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. ASAP 2007: 18-23 - 2006
- [c2]Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
An Optimized Design Approach for Squaring Large Integers Using Embedded Hardwired Multipliers. AICCSA 2006: 248-254 - [c1]Shuli Gao, Dhamin Al-Khalili, Noureddine Chabini, J. M. Pierre Langlois:
Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers. SoCC 2006: 21-24
Coauthor Index
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