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ORCIDAntonio Zenteno Ramírez
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2010 – 2019
- 2015
[c7]Antonio Zenteno Ramírez:
Power distribution network analysis using semi irregular plane shape approach and via modeling. LATS 2015: 1-6
2000 – 2009
- 2007
- [j2]Antonio Zenteno Ramírez, Guillermo Espinosa, Víctor H. Champac:
Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 15(5): 572-577 (2007) - 2005
- [c6]Víctor H. Champac, Antonio Zenteno, José L. Garcia:
Testing of resistive opens in CMOS latches and flip-flops. ETS 2005: 34-40 - 2004
- [c5]Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs:
Analysis and Attenuation Proposal in Ground Bounce. Asian Test Symposium 2004: 460-463 - 2002
- [c4]Antonio Zenteno, Víctor H. Champac, Jaime Ramírez-Angulo:
Behavior Analysis and Testing of Resistive Opens in the Clock Circuitry of Memory Elements. LATW 2002: 205-211 - 2001
- [j1]Antonio Zenteno, Víctor H. Champac, Joan Figueras:
Detectability Conditions of Full Opens in the Interconnections. J. Electron. Test. 17(2): 85-95 (2001) - [c3]Antonio Zenteno, Víctor H. Champac:
Resistive Opens in a Class of CMOS Latches: Analysis and DFT. VTS 2001: 138-144 - 2000
- [c2]Antonio Zenteno, Víctor H. Champac, Joan Figueras:
Detectability Dependency on Test Generation Process for Interconnection Opens. LATW 2000: 47-53 - [c1]Víctor H. Champac, Antonio Zenteno:
Detectability Conditions for Interconnection Open Defect. VTS 2000: 305-312
Coauthor Index
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