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2020 – today
- 2023
[c12]Yusei Horikawa, Renpei Yoshida, Seiji Mochizuki, Tetsuya Matsumura:
Clustering Re-Inference Algorithm for Deep Learning-Based Hierarchical Object Detection System. GCCE 2023: 817-818- [c11]Mai Yamaguchi, Mai Yamakawa, Seiji Mochizuki, Kousuke Imamura, Toshiki Kanamoto, Tetsuya Matsumura:
Ultra-Low-Latency Video Coding with Reduced Frame Memory Structure for 4K/8K High-Resolution Video. GCCE 2023: 852-853 - [c10]Yusei Horikawa, Seiji Mochizuki, Kousuke Imamura, Tetsuya Matsumura:
CGTI-Net: Deep-Learning-Based Object Detection Network for High-Resolution Aerial Images. IoTaIS 2023: 169-174 - 2022
- [j6]Katsushige Matsubara
, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei:
A 12-nm Autonomous Driving Processor With 60.4 TOPS, 13.8 TOPS/W CNN Executed by Task-Separated ASIL D Control. IEEE J. Solid State Circuits 57(1): 115-126 (2022) - 2021
- [c9]Katsushige Matsubara, Hanno Lieske, Motoki Kimura, Atsushi Nakamura, Manabu Koike, Kazuaki Terashima, Shun Morikawa, Yoshihiko Hotta, Takahiro Irita, Seiji Mochizuki, Hiroyuki Hamasaki, Tatsuya Kamei:
4.2 A 12nm Autonomous-Driving Processor with 60.4TOPS, 13.8TOPS/W CNN Executed by Task-Separated ASIL D Control. ISSCC 2021: 56-58
2010 – 2019
- 2019
- [c8]Kosuke Fukava, Kaito Mori, Kousuke Imamura, Yoshio Matsuda, Tetsuya Matsumura, Seiji Mochizuki:
Design and Implementation of Ultra-Low-Latency Video Encoder Using High-Level Synthesis. ISPACS 2019: 1-2 - 2018
- [c7]Seiji Mochizuki, Kousuke Imamura, Kaito Mori, Yoshio Matsuda, Tetsuya Matsumura:
Ultra-low-latency Video Coding Method for Autonomous Vehicles and Virtual Reality Devices. IOTAIS 2018: 155-161 - 2017
- [j5]Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori:
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2878-2887 (2017) - 2016
- [c6]Chi Lan Phuong Nguyen, My Phi Ngoc Nguyen, Hung Van Cao, Katsushige Matsubara, Keisuke Matsumoto, Seiji Mochizuki, Kenichi Iwata:
71% Reducing the memory bandwidth requirement for a multi-standard video codec by lossless compression of video using a combination of 2D-DPCM and Variable Length Coding. ICICDT 2016: 1-5 - [c5]Seiji Mochizuki, Katsushige Matsubara, Keisuke Matsumoto, Chi Lan Phuong Nguyen, Tetsuya Shibayama, Kenichi Iwata, Katsuya Mizumoto, Takahiro Irita, Hirotaka Hara, Toshihiro Hattori:
4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems. ISSCC 2016: 78-79 - 2012
- [c4]Kenichi Iwata, Ryoji Hashimoto, Seiji Mochizuki, Kiyoharu Aizawa:
Intra texture prediction based on repetitive pixel replenishment. ICIP 2012: 2933-2936 - 2011
- [c3]Tuan Minh Phan Ho, Thang Minh Le, Khanh Duy Vu, Seiji Mochizuki, Kenichi Iwata, Keisuke Matsumoto, Hiroshi Ueda:
A 768 Megapixels/sec inverse transform with hybrid architecture for multi-standard decoder. ASICON 2011: 71-74 - 2010
- [j4]Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori:
A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits. IEEE J. Solid State Circuits 45(1): 59-68 (2010)
2000 – 2009
- 2009
- [j3]Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Koji Hosogi, Hiroaki Nakata, Masakazu Ehama, Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe:
A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS. IEEE J. Solid State Circuits 44(4): 1184-1191 (2009) - [j2]Motoki Kimura, Kenichi Iwata, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Hiromi Watanabe:
A Full HD Multistandard Video Codec for Mobile Applications. IEEE Micro 29(6): 18-27 (2009) - [c2]Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa, Toru Fujihira, Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Masaki Nobori:
Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture. ASP-DAC 2009: 528-534 - [c1]Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori:
A 342mW mobile application processor with full-HD multi-standard video codec. ISSCC 2009: 158-159 - 2008
- [j1]Seiji Mochizuki, Tetsuya Shibayama, Masaru Hase, Fumitaka Izuhara, Kazushi Akie, Masaki Nobori, Ren Imaoka, Hiroshi Ueda, Kazuyuki Ishikawa, Hiromi Watanabe:
A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS. IEEE J. Solid State Circuits 43(11): 2354-2362 (2008)
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