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ORCIDDariusz Kania
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2020 – today
- 2024
[j21]Marcin Kubica
, Boleslaw Pochopien, Dariusz Kania:
Switching Activity Reduction of SOP Networks. IEEE Access 12: 112984-112994 (2024)- 2023
- [j20]Adam Opara, Marcin Kubica, Dariusz Kania:
Decomposition Approaches for Power Reduction. IEEE Access 11: 29417-29429 (2023) - 2022
- [j19]Tomasz Lukaszewicz, Dariusz Kania:
A Music Classification Approach Based on the Trajectory of Fifths. IEEE Access 10: 73494-73502 (2022) - 2021
- [b1]Marcin Kubica, Adam Opara, Dariusz Kania:
Technology Mapping for LUT-Based FPGA. Lecture Notes in Electrical Engineering 713, Springer 2021, ISBN 978-3-030-60487-5, pp. 1-204 - [j18]Dariusz Kania, Paulina Kania, Tomasz Lukaszewicz:
Trajectory of Fifths in Music Data Mining. IEEE Access 9: 8751-8761 (2021) - [j17]Józef Borkowski, Janusz Mroczka, Adam Matusiak, Dariusz Kania:
Frequency Estimation in Interpolated Discrete Fourier Transform With Generalized Maximum Sidelobe Decay Windows for the Control of Power. IEEE Trans. Ind. Informatics 17(3): 1614-1624 (2021)
2010 – 2019
- 2019
- [j16]Marcin Kubica, Dariusz Kania, Józef Kulisz:
A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs. IEEE Access 7: 16123-16131 (2019) - [j15]Adam Opara, Marcin Kubica, Dariusz Kania:
Methods of Improving Time Efficiency of Decomposition Dedicated at FPGA Structures and Using BDD in the Process of Cyber-Physical Synthesis. IEEE Access 7: 20619-20631 (2019) - [j14]Tomasz Lukaszewicz, Dariusz Kania, Zenon Kidon, Krystyna Pethe-Kania:
Postural Symmetry Evaluation Based on the Analysis of Temporary and Average CoP Displacements Registered During the Follow-Up Posturography. IEEE Access 7: 26402-26410 (2019) - [j13]Remigiusz Wisniewski, Grzegorz Benysek, Luís Gomes, Dariusz Kania, Theodore E. Simos, Mengchu Zhou:
IEEE Access Special Section: Cyber-Physical Systems. IEEE Access 7: 157688-157692 (2019) - [c14]Józef Borkowski, Dariusz Kania:
Simulation Comparison of Frequency Estimation Methods Applied for Power Control in Renewable Energy Systems. SMACD 2019: 273-276 - 2018
- [j12]Adam Opara, Marcin Kubica, Dariusz Kania:
Strategy of logic synthesis using MTBDD dedicated to FPGA. Integr. 62: 142-158 (2018) - [j11]Krzysztof Kajstura, Dariusz Kania:
Low Power Synthesis of Finite State Machines - State Assignment Decomposition Algorithm. J. Circuits Syst. Comput. 27(3): 1850041:1-1850041:14 (2018) - [c13]Dariusz Kania, Jozef Borkowski, Janusz Mroczka:
Influence of Noise on Multifrequency Signals for the Amplitude and Phase Estimation in Photovoltaic Systems with a DSP Processor. TSP 2018: 1-4 - 2017
- [j10]Marcin Kubica, Dariusz Kania:
Area-oriented technology mapping for LUT-based logic blocks. Int. J. Appl. Math. Comput. Sci. 27(1): 207 (2017) - [j9]Marcin Kubica, Adam Opara, Dariusz Kania:
Logic synthesis for FPGAs based on cutting of BDD. Microprocess. Microsystems 52: 173-187 (2017) - [c12]Dariusz Kania, Jozef Borkowski:
Estimation methods of multifrequency signals with noise and harmonics for PV systems with a DSP processor. TSP 2017: 524-527 - 2016
- [j8]Robert Czerwinski, Dariusz Kania:
State Assignment and Optimization of Ultra-High-Speed FSMs Utilizing Tristate Buffers. ACM Trans. Design Autom. Electr. Syst. 22(1): 3:1-3:25 (2016) - [i1]Jozef Borkowski, Dariusz Kania:
Interpolated-DFT-Based Fast and Accurate Amplitude and Phase Estimation for the Control of Power. CoRR abs/1601.00453 (2016) - 2015
- [j7]Dariusz Kania:
Logic Decomposition for PAL-Based CPLDs. J. Circuits Syst. Comput. 24(3): 1550042:1-1550042:27 (2015) - 2014
- [j6]Jozef Borkowski, Dariusz Kania, Janusz Mroczka:
Interpolated-DFT-Based Fast and Accurate Frequency Estimation for the Control of Power. IEEE Trans. Ind. Electron. 61(12): 7026-7034 (2014) - 2012
- [j5]Robert Czerwinski, Dariusz Kania:
Area and speed oriented synthesis of FSMs for PAL-based CPLDs. Microprocess. Microsystems 36(1): 45-61 (2012) - 2010
- [j4]Adam Opara, Dariusz Kania:
Decomposition-based logic synthesis for PAL-based CPLDs. Int. J. Appl. Math. Comput. Sci. 20(2): 367-384 (2010) - [j3]Dariusz Kania, Adam Milik:
Logic synthesis based on decomposition for CPLDs. Microprocess. Microsystems 34(1): 25-38 (2010)
2000 – 2009
- 2009
- [j2]Robert Czerwinski, Dariusz Kania:
Synthesis of finite state machines for CPLDs. Int. J. Appl. Math. Comput. Sci. 19(4): 647-659 (2009) - [c11]Robert Czerwinski, Dariusz Kania:
CPLD-oriented Synthesis of Finite State Machines. DSD 2009: 521-528 - [c10]Robert Czerwinski, Dariusz Kania:
State assignment and logic optimization for finite state machines. PDeS 2009: 39-44 - 2007
- [j1]Dariusz Kania, Józef Kulisz:
Logic synthesis for PAL-based CPLD-s based on two-stage decomposition. J. Syst. Softw. 80(7): 1129-1141 (2007) - [c9]Dariusz Kania:
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS. ACM Great Lakes Symposium on VLSI 2007: 152-155 - 2005
- [c8]Dariusz Kania, Józef Kulisz, Adam Milik:
A Novel Method of Two-Stage Decomposition Dedicated for PAL-based CPLDs. DSD 2005: 114-121 - [c7]Robert Czerwinski, Dariusz Kania:
State Assignment for PAL-based CPLDs. DSD 2005: 127-134 - [c6]Dariusz Kania, Adam Milik, Józef Kulisz:
Decomposition of Multi-Output Functions for CPLDs. DSD 2005: 442-449 - 2002
- [c5]Dariusz Kania:
Improved Technology Mapping for PAL-Based Devices Using a New Approach to Multi-Output Boolean Functions. DATE 2002: 1087 - [c4]Dariusz Kania:
Logic synthesis of multi-output functions for PAL-based CPLDs. FPT 2002: 429-432 - 2000
- [c3]Dariusz Kania:
Decomposition-Based Synthesis and its Application in PAL-Oriented Technology Mapping. EUROMICRO 2000: 1138-1145 - [c2]Dariusz Kania:
A Technology Mapping Algorithm for PAL-Based Devices Using Multi-Output Function Graphs. EUROMICRO 2000: 1146-
1990 – 1999
- 1999
- [c1]Dariusz Kania:
Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition. EUROMICRO 1999: 1278-1281
Coauthor Index
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last updated on 2024-09-10 01:13 CEST by the dblp team
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