default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDStephan Eggersglüß
Person information
- affiliation: Siemens Digital Industries Software, Wilsonville, OR, USA
- affiliation (former): DFKI, Bremen
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
[j11]Janusz Rajski
, Vivek Chickermane, Jean-François Côté, Stephan Eggersglüß, Nilanjan Mukherjee, Jerzy Tyszer:
The Future of Design for Test and Silicon Lifecycle Management. IEEE Des. Test 41(4): 35-49 (2024)- 2023
- [j10]Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer:
A New Static Compaction of Deterministic Test Sets. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 411-420 (2023) - 2021
- [c41]Stephan Eggersglüß, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer:
On Reduction of Deterministic Test Pattern Sets. ITC 2021: 260-267
2010 – 2019
- 2019
- [c40]Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler:
Machine Learning-based Prediction of Test Power. ETS 2019: 1-6 - [c39]Stephan Eggersglüß:
Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques. ITC 2019: 1-8 - [c38]Stephan Eggersglüß, Said Hamdioui, Artur Jutman, Maria K. Michael, Jaan Raik, Matteo Sonza Reorda, Mehdi Baradaran Tahoori, Elena Ioana Vatajelu:
IEEE European Test Symposium (ETS). ITC 2019: 1-4 - [c37]Stephan Eggersglüß:
Towards Complete Fault Coverage by Test Point Insertion using Optimization-SAT Techniques. ITC-Asia 2019: 67-72 - [c36]Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler:
Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements. LATS 2019: 1-4 - 2018
- [c35]Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler:
Approximation-aware testing for approximate circuits. ASP-DAC 2018: 239-244 - [c34]Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen:
Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing. DDECS 2018: 79-84 - 2017
- [c33]Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler:
Identification of Efficient Clustering Techniques for Test Power Activity on the Layout. ATS 2017: 108-113 - [c32]Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler:
Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. DATE 2017: 578-583 - [c31]Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler:
Machine learning based test pattern analysis for localizing critical power activity areas. DFT 2017: 1-6 - [c30]Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler:
Reconfigurable TAP controllers with embedded compression for large test data volume. DFT 2017: 1-6 - [c29]Maria K. Michael, Rolf Drechsler, Stephan Eggersglüß, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken:
Foreword. ETS 2017: 1-2 - [c28]Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler:
Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements. SSCI 2017: 1-6 - 2016
- [j9]Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler:
On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2104-2117 (2016) - [c27]Stephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen:
Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test. ATS 2016: 173-178 - [c26]Stephan Eggersglüß, Kohei Miyase, Xiaoqing Wen:
SAT-based post-processing for regional capture power reduction in at-speed scan test generation. ETS 2016: 1-6 - [c25]Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler:
VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. ETS 2016: 1-6 - [c24]Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler:
Exploring superior structural materials using multi-objective optimization and formal techniques. ISED 2016: 13-17 - 2015
- [c23]Stephan Eggersglüß:
Compact test set generation for test compression-based designs. ETS 2015: 1-6 - 2014
- [j8]Stephan Eggersglüß:
Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets. J. Electron. Test. 30(5): 557-567 (2014) - [j7]Stephan Eggersglüß, Rolf Drechsler:
An effective fault ordering heuristic for SAT-based dynamic test compaction techniques. it Inf. Technol. 56(4): 157-164 (2014) - [c22]Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer:
Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization. DTIS 2014: 1-10 - [c21]Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler:
Optimization-based multiple target test generation for highly compacted test sets. ETS 2014: 1-6 - [c20]Mehdi Dehbashi, Daniel Tille, Ulrike Pfannkuchen, Stephan Eggersglüß:
Automated formal verification of X propagation with respect to testability issues. IDT 2014: 106-111 - 2013
- [c19]Stephan Eggersglüß:
Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill. Asian Test Symposium 2013: 31-36 - [c18]Stephan Eggersglüß, Robert Wille, Rolf Drechsler:
Improved SAT-based ATPG: more constraints, better compaction. ICCAD 2013: 85-90 - [c17]Rolf Drechsler, Melanie Diepenbeck, Stephan Eggersglüß, Robert Wille:
PASSAT 2.0: A multi-functional SAT-based testing framework. LATW 2013: 1 - 2012
- [b3]Stephan Eggersglüß, Rolf Drechsler:
High Quality Test Pattern Generation and Boolean Satisfiability. Springer 2012, ISBN 978-1-4419-9975-7, pp. I-XVIII, 1-193 - [j6]Stephan Eggersglüß, Rolf Drechsler:
A Highly Fault-Efficient SAT-Based ATPG Flow. IEEE Des. Test Comput. 29(4): 63-70 (2012) - [c16]Stephan Eggersglüß, Mahmut Yilmaz, Krishnendu Chakrabarty:
Robust Timing-Aware Test Generation Using Pseudo-Boolean Optimization. Asian Test Symposium 2012: 290-295 - [c15]Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler:
A new SAT-based ATPG for generating highly compacted test sets. DDECS 2012: 230-235 - 2011
- [j5]Stephan Eggersglüß, Rolf Drechsler:
Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1411-1415 (2011) - [c14]Stephan Eggersglüß, Rolf Drechsler:
As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. DATE 2011: 1291-1296 - 2010
- [b2]Stephan Eggersglüß:
Robust algorithms for high quality test pattern generation using Boolean satisfiability. University of Bremen, 2010, pp. 1-182 - [j4]Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler:
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electron. Test. 26(3): 307-322 (2010) - [j3]Daniel Tille, Stephan Eggersglüß, Rolf Drechsler:
Incremental Solving Techniques for SAT-based ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1125-1130 (2010) - [c13]Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler:
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. ETS 2010: 176-181 - [c12]Stephan Eggersglüß, Daniel Tille, Rolf Drechsler:
Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. ISCAS 2010: 649-652 - [p1]Stephan Eggersglüß:
Robuste Erfüllbarkeitsalgorithmen zur Generierung hochwertiger Testmuster für digitale Schaltungen. Ausgezeichnete Informatikdissertationen 2010: 81-90
2000 – 2009
- 2009
- [b1]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille:
Test Pattern Generation using Boolean Proof Engines. Springer 2009, ISBN 978-90-481-2359-9, pp. I-XII, 1-192 - [j2]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille:
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it Inf. Technol. 51(2): 102-111 (2009) - [c11]Stephan Eggersglüß, Daniel Tille, Rolf Drechsler:
Speeding up SAT-Based ATPG Using Dynamic Clause Activation. Asian Test Symposium 2009: 177-182 - [c10]Stephan Eggersglüß, Rolf Drechsler:
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. ETS 2009: 81-86 - [c9]Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler:
Timing Arc based logic analysis for false noise reduction. ICCAD 2009: 225-230 - 2008
- [j1]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille:
On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1329-1333 (2008) - [c8]Stephan Eggersglüß, Rolf Drechsler:
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. ISMVL 2008: 94-99 - [i1]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille:
SAT-based Automatic Test Pattern Generation. Evolutionary Test Generation 2008 - 2007
- [c7]Stephan Eggersglüß, Rolf Drechsler:
Improving Test Pattern Compactness in SAT-based ATPG. ATS 2007: 445-452 - [c6]Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler:
SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS 2007: 3671-3674 - [c5]Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6 - [c4]Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler:
Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV 2007: 81-90 - [c3]Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE 2007: 181-187 - [c2]Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler:
SWORD: A SAT like Prover Using Word Level Information. VLSI-SoC (Selected Papers) 2007: 1-17 - [c1]Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler:
SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-08-03 20:15 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
