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ORCIDAmir Amirkhany
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2020 – today
- 2022
[j10]Amir Amirkhany
, Tanay Karnik, Shidhartha Das, Jun Deguchi, Yasuhiko Taito:
Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 57(1): 3-5 (2022)- [j9]Tianyu Wang, Da Wei, Ranick Ng, Gaurav Malhotra, Anup P. Jose, Amir Amirkhany, Pavan Kumar Hanumolu:
A 5.2 Gb/s Receiver for Next-Generation 8K Displays in 180 nm CMOS Process. IEEE J. Solid State Circuits 57(8): 2521-2531 (2022) - 2021
- [c17]Gaurav Malhotra, Jalil Kamali, Amir Amirkhany:
Baud rate pattern-adaptable dual loop clock recovery for high speed serial links. ACSCC 2021: 43-48 - [c16]Mike Shuo-Wei Chen, Wei-Zen Chen, Amir Amirkhany:
Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee. ISSCC 2021: 178-179
2010 – 2019
- 2019
- [c15]Anup P. Jose, Valentin Abramzon, Mohamed Elzeftawi, Michael Wang, Kyunglok Kim, Younghoon Song, Shiva Moballegh, Jalil Kamali, Amir Amirkhany:
A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process. CICC 2019: 1-4 - 2016
- [c14]Mohammad Hekmat, Sanquan Song, Nancy Jaffari, Sabarish Sankaranarayanan, Chaofeng Huang, Minghui Han, Gaurav Malhotra, Jalil Kamali, Amir Amirkhany, Wei Xiong:
23.3 A 6Gb/s 3-tap FFE transmitter and 5-tap DFE receiver in 65nm/0.18µm CMOS for next-generation 8K displays. ISSCC 2016: 402-403 - 2013
- [j8]Kambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Wendemagegnehu T. Beyene, Chris J. Madden, Keisuke Saito, Koji Sano, Vinod Inipodu Murugan, Kun-Yung Ken Chang, Xingchao Chuck Yuan:
A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver. IEEE J. Solid State Circuits 48(3): 636-648 (2013) - [c13]Kwangmo Jung, Amir Amirkhany, Kambiz Kaviani:
A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS. ISSCC 2013: 42-43 - 2012
- [j7]Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan:
A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. IEEE J. Solid State Circuits 47(4): 911-925 (2012) - [j6]Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan:
A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. IEEE J. Solid State Circuits 47(4): 926-937 (2012) - [j5]Amir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris J. Madden, Ken Chang, Chuck Yuan:
A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link. IEEE J. Solid State Circuits 47(12): 3208-3219 (2012) - [c12]Kambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Chris J. Madden, Keisuke Saito, Koji Sano, Vinod Murugan, Wendemagegnehu T. Beyene, Ken Chang, Chuck Yuan:
A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration. ISSCC 2012: 132-134 - [c11]Amir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris J. Madden, Ken Chang, Chuck Yuan:
A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link. ISSCC 2012: 138-140 - 2011
- [c10]Amir Amirkhany, Wendemagegnehu T. Beyene, Chris J. Madden, Aliazam Abbasfar, Dave Secker, Dan Oh, Mohammad Hekmat, Ralf Schmitt, Chuck Yuan:
On overcoming the limitations of single-ended signaling for graphics memory interfaces. A-SSCC 2011: 25-28 - [c9]John C. Eble, Scott Best, Brian S. Leibowitz, Lei Luo, Robert Palmer, John M. Wilson, Jared Zerbe, Amir Amirkhany, Nhat Nguyen:
Power-efficient I/O design considerations for high-bandwidth applications. CICC 2011: 1-8 - [c8]Navin K. Mishra, Manish Jain, Phuong Le, Sanku Mukherjee, Arul Sendhil, Amir Amirkhany:
An output structure for a bi-modal 6.4-Gbps GDDR5 and 2.4-Gbps DDR3 compatible memory interface. CICC 2011: 1-4 - 2010
- [j4]Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani:
A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links. IEEE J. Solid State Circuits 45(8): 1533-1541 (2010) - [j3]Farshid Aryanfar, Amir Amirkhany:
A Low-Cost Resonance Mitigation Technique for Multidrop Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 57-II(5): 339-342 (2010)
2000 – 2009
- 2009
- [c7]Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani:
A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links. CICC 2009: 125-128 - 2008
- [j2]Amir Amirkhany, Aliazam Abbasfar, Jafar Savoj, Metha Jeeradit, Bruno W. Garlepp, Ravi T. Kollipara, Vladimir Stojanovic, Mark Horowitz:
A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter. IEEE J. Solid State Circuits 43(4): 999-1009 (2008) - [j1]Jafar Savoj, Aliazam Abbasfar, Amir Amirkhany, Metha Jeeradit, Bruno W. Garlepp:
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications. IEEE J. Solid State Circuits 43(5): 1207-1216 (2008) - 2007
- [c6]Amir Amirkhany, Ali-Azam Abbasfar, Jafar Savoj, Mark A. Horowitz:
Time-Variant Characterization and Compensation of Wideband Circuits. CICC 2007: 487-490 - [c5]Jafar Savoj, Ali-Azam Abbasfar, Amir Amirkhany, Bruno W. Garlepp, Mark A. Horowitz:
A new technique for characterization of digital-to-analog converters in high-speed systems. DATE 2007: 433-438 - [c4]Amir Amirkhany, Ali-Azam Abbasfar, Vladimir Stojanovic, Mark A. Horowitz:
Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links. ICC 2007: 2693-2698 - 2006
- [c3]Amir Amirkhany, Ali-Azam Abbasfar, Vladimir Stojanovic, Mark A. Horowitz:
Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links. GLOBECOM 2006 - 2004
- [c2]Amir Amirkhany, Vladimir Stojanovic, Mark A. Horowitz:
Multi-tone signaling for high-speed backplane electrical links. GLOBECOM 2004: 1111-1117 - [c1]Vladimir Stojanovic, Amir Amirkhany, Mark A. Horowitz:
Optimal linear precoding with theoretical and practical data rates in high-speed serial-link backplane communication. ICC 2004: 2799-2806
Coauthor Index
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