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2020 – today
- 2024
[j95]Boseon Jang
, Hyejung Jang, Sungho Kim, Kangjoon Choi, In-Cheol Park:
Area-Efficient QC-LDPC Decoding Architecture With Thermometer Code-Based Sorting and Relative Quasi-Cyclic Shifting. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2897-2910 (2024)- [j94]Jeongmin Kim, Sungho Kim, Kangjoon Choi, In-Cheol Park:
Hardware-Efficient SoftMax Architecture With Bit-Wise Exponentiation and Reciprocal Calculation. IEEE Trans. Circuits Syst. I Regul. Pap. 71(10): 4574-4585 (2024) - [j93]Kangjoon Choi, Sungho Kim, Jeongmin Kim, In-Cheol Park:
Hardware-Friendly Approximation for Swish Activation and Its Implementation. IEEE Trans. Circuits Syst. II Express Briefs 71(10): 4516-4520 (2024) - 2023
- [j92]Hyungjoon Bae, Yujin Hyun, Suchang Kim, Sangsoo Park, Jaeyoung Lee, Boseon Jang, Suyoung Choi, In-Cheol Park:
High-Speed Counter With Novel LFSR State Extension. IEEE Trans. Computers 72(3): 893-899 (2023) - [j91]Suchang Kim, Boseon Jang, Jaeyoung Lee, Hyungjoon Bae, Hyejung Jang, In-Cheol Park:
A CNN Inference Accelerator on FPGA With Compression and Layer-Chaining Techniques for Style Transfer Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70(4): 1591-1604 (2023) - 2022
- [j90]Jaehyeon Park, Jaeyoung Lee, In-Cheol Park:
In Situ Multi-Bit Decision for Successive Cancellation List Decoding of Polar Codes. IEEE Access 10: 86943-86952 (2022) - [j89]Seongjin Lee, Sangsoo Park, Boseon Jang, In-Cheol Park:
Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard. IEEE Trans. Circuits Syst. I Regul. Pap. 69(5): 2035-2048 (2022) - 2021
- [j88]Wooyoung Kim, Yujin Hyun, Jaeyoung Lee, In-Cheol Park:
Interleaved Local Sorting for Successive Cancellation List Decoding of Polar Codes. IEEE Access 9: 128623-128632 (2021) - [j87]Suchang Kim, Jihyuck Jo, In-Cheol Park:
Hybrid Convolution Architecture for Energy-Efficient Deep Neural Network Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 2017-2029 (2021) - [j86]Yujin Hyun, In-Cheol Park:
Constant-Time Synchronous Binary Counter With Minimal Clock Period. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2645-2649 (2021) - [j85]Suchang Kim, Seungho Na, Byeong Yong Kong, Jaewoong Choi, In-Cheol Park:
Real-Time SSDLite Object Detection on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1192-1205 (2021) - 2020
- [j84]Kyungpil Lee, In-Cheol Park:
Large-Small Sorting for Successive Cancellation List Decoding of Polar Codes. IEEE Access 8: 96955-96962 (2020) - [j83]Byeong Yong Kong, Jooseung Lee, In-Cheol Park:
A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 166-176 (2020) - [j82]Byeong Yong Kong, In-Cheol Park:
A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access. IEEE Trans. Circuits Syst. II Express Briefs 67-II(3): 470-474 (2020) - [j81]Jaewoong Choi, Byeong Yong Kong, In-Cheol Park:
Retrain-Less Weight Quantization for Multiplier-Less Convolutional Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(3): 972-982 (2020) - [c105]Byeong Yong Kong, Jooseung Lee, In-Cheol Park:
A Low-Latency Multi-Touch Detector Based on Concurrent Processing of Redesigned Overlap Split and Connected Component Analysis. ISCAS 2020: 1 - [c104]Byeong Yong Kong, In-Cheol Park:
A 120-mW 0.16-ms-Latency Connectivity-Scalable Multiuser Detector for Interleave Division Multiple Access. ISCAS 2020: 1
2010 – 2019
- 2019
- [j80]Seokha Hwang, Seungsik Moon, Jaehwan Jung, Daesung Kim, In-Cheol Park, Jeongseok Ha, Youngjoo Lee:
Energy-Efficient Symmetric BC-BCH Decoder Architecture for Mobile Storages. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(11): 4462-4475 (2019) - [c103]Byeong Yong Kong, In-Cheol Park:
Parallel IDMA Architecture Based on Interleaving with Replicated Subpatterns. ICC 2019: 1-6 - 2018
- [j79]Jihyuck Jo, Soyoung Cha, Dayoung Rho, In-Cheol Park:
DSIP: A Scalable Inference Accelerator for Convolutional Neural Networks. IEEE J. Solid State Circuits 53(2): 605-618 (2018) - [j78]Byeong Yong Kong, In-Cheol Park:
A Memory-Efficient IDMA Architecture Based on On-the-Fly Despreading. IEEE J. Solid State Circuits 53(11): 3327-3337 (2018) - [j77]Daesung Kim, Injae Yoo, In-Cheol Park:
Fast Low-Complexity Triple-Error-Correcting BCH Decoding Architecture. IEEE Trans. Circuits Syst. II Express Briefs 65-II(6): 764-768 (2018) - [j76]Jihyuck Jo, Suchang Kim, In-Cheol Park:
Energy-Efficient Convolution Architecture Based on Rescheduled Dataflow. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4196-4207 (2018) - [j75]Daesung Kim, In-Cheol Park:
A Fast Successive Cancellation List Decoder for Polar Codes With an Early Stopping Criterion. IEEE Trans. Signal Process. 66(18): 4971-4979 (2018) - [c102]Jaehwan Jung, In-Cheol Park, Youngjoo Lee:
A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH decoder in 65nm CMOS for NAND flash storage systems. ASP-DAC 2018: 329-330 - [c101]Byeong Yong Kong, Jaehwan Jung, In-Cheol Park:
Interference Cancellation Architecture for Pipelined Parallel MIMO Detectors. ICECS 2018: 77-80 - [c100]Byeong Yong Kong, In-Cheol Park:
Efficient Implementation of Multiple Interleavers in IDMA for 5G. ISOCC 2018: 119-120 - 2017
- [j74]Saedong Yeo, In-Cheol Park:
Improved Hard-Reliability Based Majority-Logic Decoding for Non-Binary LDPC Codes. IEEE Commun. Lett. 21(1): 230-233 (2017) - [j73]Jaehwan Jung, In-Cheol Park:
Multi-Bit Flipping Decoding of LDPC Codes for NAND Storage Systems. IEEE Commun. Lett. 21(5): 979-982 (2017) - [j72]Jaejoon Choi, In-Cheol Park:
Improved Successive-Cancellation Decoding of Polar Codes Based on Recursive Syndrome Decomposition. IEEE Commun. Lett. 21(11): 2344-2347 (2017) - [j71]Jihyuck Jo, In-Cheol Park:
Low-Latency Low-Cost Architecture for Square and Cube Roots. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(9): 1951-1955 (2017) - [j70]Jooseung Lee, In-Cheol Park:
High-Performance Low-Area Video Up-Scaling Architecture for 4-K UHD Video. IEEE Trans. Circuits Syst. II Express Briefs 64-II(4): 437-441 (2017) - [j69]Byeong Yong Kong, In-Cheol Park:
Improved Sorting Architecture for K-Best MIMO Detection. IEEE Trans. Circuits Syst. II Express Briefs 64-II(9): 1042-1046 (2017) - [j68]Injae Yoo, In-Cheol Park:
Low-Power LDPC-CC Decoding Architecture Based on the Integration of Memory Banks. IEEE Trans. Circuits Syst. II Express Briefs 64-II(9): 1057-1061 (2017) - [c99]Seokha Hwang, Jaehwan Jung, Daesung Kim, Jeongseok Ha, In-Cheol Park, Youngjoo Lee:
An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages. A-SSCC 2017: 169-172 - 2016
- [j67]Hoyoung Yoo, In-Cheol Park:
Efficient Pruning for Successive-Cancellation Decoding of Polar Codes. IEEE Commun. Lett. 20(12): 2362-2365 (2016) - [j66]Youngjoo Lee, Jaehwan Jung, In-Cheol Park:
Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems. IEICE Trans. Electron. 99-C(2): 293-301 (2016) - [j65]Hoyoung Yoo, Youngjoo Lee, In-Cheol Park:
Low-Power Parallel Chien Search Architecture Using a Two-Step Approach. IEEE Trans. Circuits Syst. II Express Briefs 63-II(3): 269-273 (2016) - [j64]Byeong Yong Kong, Hoyoung Yoo, In-Cheol Park:
Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes. IEEE Trans. Circuits Syst. II Express Briefs 63-II(7): 673-677 (2016) - [j63]Jaejoon Choi, Jaehwan Jung, In-Cheol Park:
Area-Efficient Approach for Generating Quantized Gaussian Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(7): 1005-1013 (2016) - [j62]Jihyuck Jo, Hoyoung Yoo, In-Cheol Park:
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 754-758 (2016) - [c98]Byeong Yong Kong, In-Cheol Park:
Low-complexity symbol detection for massive MIMO uplink based on Jacobi method. PIMRC 2016: 1-5 - 2015
- [j61]Youngjoo Lee, Bongjin Kim, Jaehwan Jung, In-Cheol Park:
Low-Complexity Tree Architecture for Finding the First Two Minima. IEEE Trans. Circuits Syst. II Express Briefs 62-II(1): 61-64 (2015) - [j60]Hoyoung Yoo, In-Cheol Park:
Partially Parallel Encoder Architecture for Long Polar Codes. IEEE Trans. Circuits Syst. II Express Briefs 62-II(3): 306-310 (2015) - [j59]Jaehwan Jung, Hoyoung Yoo, Youngjoo Lee, In-Cheol Park:
Efficient Parallel Architecture for Linear Feedback Shift Registers. IEEE Trans. Circuits Syst. II Express Briefs 62-II(11): 1068-1072 (2015) - [j58]Injae Yoo, Bongjin Kim, In-Cheol Park:
Reverse Rate Matching for Low-Power LTE-Advanced Turbo Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(12): 2920-2928 (2015) - [c97]Byeong Yong Kong, In-Cheol Park:
Narrow-range frequency estimation based on comprehensive optimization of DFT and interpolation. ICASSP 2015: 2609-2613 - [c96]Injae Yoo, Mina Hwang, Jaehwan Jung, Suhyun Kim, In-Cheol Park:
Unidirectional ring ethernet for low-complexity in-vehicle control network. ICIT 2015: 1951-1955 - 2014
- [j57]Injae Yoo, Bongjin Kim, In-Cheol Park:
Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(9): 2711-2720 (2014) - [j56]Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park:
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives. IEEE Trans. Very Large Scale Integr. Syst. 22(5): 1183-1187 (2014) - [j55]Byeong Yong Kong, Jihyuck Jo, Hyewon Jeong, Mina Hwang, Soyoung Cha, Bongjin Kim, In-Cheol Park:
Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes. IEEE Trans. Very Large Scale Integr. Syst. 22(7): 1648-1652 (2014) - [c95]Hoyoung Yoo, Youngjoo Lee, In-Cheol Park:
7.3 Gb/s universal BCH encoder and decoder for SSD controllers. ASP-DAC 2014: 37-38 - [c94]Injae Yoo, In-Cheol Park:
A search-less DEC BCH decoder for low-complexity fault-tolerant systems. SiPS 2014: 44-49 - 2013
- [j54]Byeong Yong Kong, In-Cheol Park:
Efficient Tree-Traversal Strategy for Soft-Output MIMO Detection Based on Candidate-Set Reorganization. IEEE Commun. Lett. 17(9): 1758-1761 (2013) - [j53]Bongjin Kim, In-Cheol Park:
Area-Efficient QC-LDPC Decoder Architecture Based on Stride Scheduling and Memory Bank Division. IEICE Trans. Commun. 96-B(7): 1772-1779 (2013) - [j52]Youngjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park:
A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash Memory. IEEE J. Solid State Circuits 48(10): 2531-2540 (2013) - [j51]Bongjin Kim, Injae Yoo, In-Cheol Park:
Low-Complexity Parallel QPP Interleaver Based on Permutation Patterns. IEEE Trans. Circuits Syst. II Express Briefs 60-II(3): 162-166 (2013) - [j50]Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park:
Area-Efficient Multimode Encoding Architecture for Long BCH Codes. IEEE Trans. Circuits Syst. II Express Briefs 60-II(12): 872-876 (2013) - [c93]Youngjoo Lee, Hoyoung Yoo, In-Cheol Park:
A 3Gb/s 2.08mm2 100b error-correcting BCH decoder in 0.13µm CMOS process. ASP-DAC 2013: 85-86 - [c92]Byeong Yong Kong, In-Cheol Park:
Adaptive Metric Calculation for Improving Detection Capability of MIMO Detectors. VTC Spring 2013: 1-5 - [c91]Injae Yoo, Bongjin Kim, In-Cheol Park:
Memory-Optimized Hybrid Decoding Method for Multi-Rate Turbo Codes. VTC Spring 2013: 1-5 - 2012
- [j49]Injae Yoo, Bongjin Kim, In-Cheol Park:
Immediate Exchange of Extrinsic Information for High-Throughput Turbo Decoding. IEEE Commun. Lett. 16(12): 2048-2051 (2012) - [j48]Byeong Yong Kong, In-Cheol Park:
FIR Filter Synthesis Based on Interleaved Processing of Coefficient Generation and Multiplier-Block Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(8): 1169-1179 (2012) - [j47]Kangwoo Park, In-Cheol Park:
Low-Complexity Tone Reservation for PAPR Reduction in OFDM Communication Systems. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1919-1923 (2012) - [c90]Youngjoo Lee, Hoyoung Yoo, In-Cheol Park:
Small-area parallel syndrome calculation for strong BCH decoding. ICASSP 2012: 1609-1612 - [c89]Hoyoung Yoo, Youngjoo Lee, In-Cheol Park:
Low-latency area-efficient decoding architecture for shortened reed-solomon codes. ISOCC 2012: 223-226 - [c88]Youngjoo Lee, Hoyoung Yoo, Injae Yoo, In-Cheol Park:
6.4Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers. ISSCC 2012: 426-428 - [c87]Injae Yoo, In-Cheol Park:
SNR-Adaptive Input Quantization for Turbo Decoding. VTC Spring 2012: 1-5 - 2011
- [j46]Tae-Hwan Kim, In-Cheol Park:
Efficient Pruning for Infinity-Norm Sphere Decoding Based on Schnorr-Euchner Enumeration. IEICE Trans. Commun. 94-B(9): 2677-2680 (2011) - [j45]Youngjoo Lee, Hoyoung Yoo, In-Cheol Park:
Low-Complexity Parallel Chien Search Structure Using Two-Dimensional Optimization. IEEE Trans. Circuits Syst. II Express Briefs 58-II(8): 522-526 (2011) - [c86]Bongjin Kim, In-Cheol Park:
QC-LDPC Decoding Architecture based on Stride Scheduling. ISCAS 2011: 1319-1322 - [c85]Jinook Song, In-Cheol Park:
Division-less high-radix interleaved modular multiplication using a scaled modulus. ISOCC 2011: 215-218 - [c84]Youngjoo Lee, Jinook Song, In-Cheol Park:
Statistical modeling of capacitor mismatch effects for successive approximation register ADCs. ISOCC 2011: 302-305 - 2010
- [j44]In-Cheol Park, Tae-Hwan Kim:
Multiplier-less and Table-less Linear Approximation for Square-Related Functions. IEICE Trans. Inf. Syst. 93-D(11): 2979-2988 (2010) - [j43]Tae-Hwan Kim, In-Cheol Park:
High-Throughput and Area-Efficient MIMO Symbol Detection Based on Modified Dijkstra's Search. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1756-1766 (2010) - [j42]Jinook Song, In-Cheol Park:
Spur-Free MASH Delta-Sigma Modulation. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(9): 2426-2437 (2010) - [j41]Tae-Hwan Kim, In-Cheol Park:
Small-Area and Low-Energy K -Best MIMO Detector Using Relaxed Tree Expansion and Early Forwarding. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(10): 2753-2761 (2010) - [j40]Minsoo Rhu, In-Cheol Park:
Optimization of Arithmetic Coding for JPEG2000. IEEE Trans. Circuits Syst. Video Technol. 20(3): 446-451 (2010) - [j39]Tae-Hwan Kim, Youngjoo Lee, In-Cheol Park:
Design of a Scalable and Programmable Sound Synthesizer. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 875-886 (2010) - [c83]Tae-Hwan Kim, In-Cheol Park:
A 2.6Gb/s 1.56mm2 near-optimal MIMO detector in 0.18µm CMOS. CICC 2010: 1-4 - [c82]Youngjoo Lee, Goeun Lim, In-Cheol Park:
Low-complex BPSK demodulation using absolute comparison. ICECS 2010: 1080-1083 - [c81]Bongjin Kim, Hasan Ahmed, In-Cheol Park:
Dual-rail decoding of low-density parity-check codes. ISCAS 2010: 477-480 - [c80]Youngjoo Lee, In-Cheol Park:
Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters. ISCAS 2010: 1464-1467 - [c79]Kangwoo Park, In-Cheol Park:
Low-complexity tone reservation method for PAPR reduction of OFDM systems. ISCAS 2010: 2147-2150 - [c78]Tae-Hwan Kim, In-Cheol Park:
Small-area and low-energy K-best MIMO detector using relaxed tree expansion and early forwarding. ISLPED 2010: 231-236
2000 – 2009
- 2009
- [j38]Ji-Hoon Kim, In-Cheol Park:
Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes. IEEE Trans. Circuits Syst. II Express Briefs 56-II(1): 81-85 (2009) - [j37]Jinook Song, In-Cheol Park:
Pipelined Discrete Wavelet Transform Architecture Scanning Dual Lines. IEEE Trans. Circuits Syst. II Express Briefs 56-II(12): 916-920 (2009) - [c77]Ji-Hoon Kim, In-Cheol Park:
A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE. CICC 2009: 487-490 - [c76]Tae-Hwan Kim, In-Cheol Park:
Implementation of a High-Throughput and Area-Efficient MIMO Detector Based on Modified Dijkstra's Search. GLOBECOM 2009: 1-6 - [c75]In-Cheol Park, Tae-Hwan Kim:
Multiplier-less and table-less linear approximation for square and square-root. ICCD 2009: 378-383 - [c74]Minsoo Rhu, In-Cheol Park:
Architecture design of a high-performance dual-symbol binary arithmetic coder for JPEG2000. ICIP 2009: 2665-2668 - [c73]Minsoo Rhu, In-Cheol Park:
Memory-less bit-plane coder architecture for JPEG2000 with concurrent column-stripe coding. ICIP 2009: 2673-2676 - [c72]Jinook Song, In-Cheol Park:
Novel Pipelined DWT Architecture for Dual-line Scan. ISCAS 2009: 373-376 - [c71]Tae-Hwan Kim, Youngjoo Lee, In-Cheol Park:
A Scalable and Programmable Sound Synthesizer. ISCAS 2009: 1855-1858 - [c70]Kangwoo Park, In-Cheol Park:
Fast Frequency Acquisition Phase Frequency Detectors with Prediction-based edge Blocking. ISCAS 2009: 1891-1894 - [c69]Minsoo Rhu, In-Cheol Park:
A novel trace-pipelined binary arithmetic coder architecture for JPEG2000. SiPS 2009: 243-248 - 2008
- [j36]Jeong-Ho Han, In-Cheol Park:
FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 958-962 (2008) - [j35]Ji-Hoon Kim, In-Cheol Park:
Double-Binary Circular Turbo Decoding Based on Border Metric Encoding. IEEE Trans. Circuits Syst. II Express Briefs 55-II(1): 79-83 (2008) - [j34]Tae-Hwan Kim, In-Cheol Park:
Low-Power and High-Accurate Synchronization for IEEE 802.16d Systems. IEEE Trans. Very Large Scale Integr. Syst. 16(12): 1620-1630 (2008) - [c68]Ji-Hoon Kim, In-Cheol Park:
Duo-binary circular turbo decoder based on border metric encoding for WiMAX. ASP-DAC 2008: 109-110 - [c67]Tae-Hwan Kim, In-Cheol Park:
Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems. ASP-DAC 2008: 111-112 - [c66]Jeong-Ho Han, In-Cheol Park:
Digital filter synthesis considering multiple adder graphs for a coefficient. ICCD 2008: 315-320 - [c65]WonHee Son, In-Cheol Park:
Prediction-based real-time CABAC decoder for high definition H.264/AVC. ISCAS 2008: 33-36 - [c64]Jeong-Sup Lee, In-Cheol Park:
Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters. ISCAS 2008: 236-239 - [c63]Hae-Soo Jeon, Duk-Hyun You, In-Cheol Park:
Fast frequency acquisition all-digital PLL using PVT calibration. ISCAS 2008: 2625-2628 - [c62]Tae-Hwan Kim, In-Cheol Park:
Time-Domain Joint Estimation of Fine Symbol Timing Offset and Integer Carrier Frequency Offset. VTC Spring 2008: 1186-1190 - 2007
- [j33]Chung-Hyo Kim, In-Cheol Park:
Parallel Decoding of Context-Based Adaptive Binary Arithmetic Codes Based on Most Probable Symbol Prediction. IEICE Trans. Inf. Syst. 90-D(2): 609-612 (2007) - [j32]Ji-Hoon Kim, In-Cheol Park:
Long-Point FFT Processing Based on Twiddle Factor Table Reduction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(11): 2526-2532 (2007) - [j31]Hyun-Yong Lee, In-Cheol Park:
Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(4): 889-900 (2007) - [j30]Sung-Won Lee, Ki-Seok Kwon, In-Cheol Park:
Pipelined Cartesian-to-Polar Coordinate Conversion Based on SRT Division. IEEE Trans. Circuits Syst. II Express Briefs 54-II(8): 680-684 (2007) - [j29]Y. Yi, In-Cheol Park:
High-Speed H.264/AVC CABAC Decoding. IEEE Trans. Circuits Syst. Video Technol. 17(4): 490-494 (2007) - [j28]Myoung-Cheol Shin, In-Cheol Park:
SIMD Processor-Based Turbo Decoder Supporting Multiple Third-Generation Wireless Standards. IEEE Trans. Very Large Scale Integr. Syst. 15(7): 801-810 (2007) - [c61]In-Cheol Park, WonHee Son, Ji-Hoon Kim:
Twiddle factor transformation for pipelined FFT processing. ICCD 2007: 1-6 - [c60]Se-Hyeon Kang, In-Cheol Park:
High Speed Sphere Decoding Based on Vertically Incremental Computation. ISCAS 2007: 665-668 - [c59]Ji-Hoon Kim, In-Cheol Park:
Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric Encoding. ISCAS 2007: 1325-1328 - [c58]Jung-Wook Kim, Jinook Song, Seokho Lee, In-Cheol Park:
Tiled Interleaving for Multi-Level 2-D Discrete Wavelet Transform. ISCAS 2007: 3984-3987 - [c57]Tae-Hwan Kim, In-Cheol Park:
Two-Step Aprroach for Coarse Time Synchronization and Frequency Offset Estimation for IEEE 802.16D Systems. SiPS 2007: 193-198 - [c56]Se-Hyeon Kang, In-Cheol Park:
Fast and Area-Efficient Sphere Decoding Using Look-Ahead Search. VTC Spring 2007: 2384-2388 - 2006
- [j27]Hye-Mi Choi, Ji-Hoon Kim, In-Cheol Park:
Low-Power Hybrid Turbo Decoding Based on Reverse Calculation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(3): 782-789 (2006) - [j26]Se-Hyeon Kang, In-Cheol Park:
Loosely coupled memory-based decoding architecture for low density parity check codes. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 1045-1056 (2006) - [j25]Dong-Soo Lee, In-Cheol Park:
Low-power log-MAP decoding based on reduced metric memory access. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(6): 1244-1253 (2006) - [c55]Hye-Mi Choi, Ji-Hoon Kim, In-Cheol Park:
Low-power hybrid turbo decoding based on reverse calculation. ISCAS 2006 - [c54]Chung-Hyo Kim, In-Cheol Park:
High speed decoding of context-based adaptive binary arithmetic codes using most probable symbol prediction. ISCAS 2006 - [c53]Kimo Kim, In-Cheol Park:
Combined image signal processing for CMOS image sensors. ISCAS 2006 - 2005
- [j24]Dong-Soo Lee, In-Cheol Park:
A Low-Complexity Stopping Criterion for Iterative Turbo Decoding. IEICE Trans. Commun. 88-B(1): 399-401 (2005) - [j23]Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
A third-order ΣΔ modulator in 0.18-μm CMOS with calibrated mixed-mode integrators. IEEE J. Solid State Circuits 40(4): 918-925 (2005) - [j22]Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators". IEEE J. Solid State Circuits 40(11): 2339 (2005) - [j21]Jong-Yeol Lee, Seong Ik Cho, In-Cheol Park:
Performance enhancement of embedded software based on new register allocation technique. Microprocess. Microsystems 29(4): 177-187 (2005) - [j20]Hyeong-Ju Kang, In-Cheol Park:
SAT-based unbounded symbolic model checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 129-140 (2005) - [j19]Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
Hybrid ΣΔ modulators with adaptive calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(5): 885-893 (2005) - [c52]Se-Hyeon Kang, In-Cheol Park:
Loosely coupled memory-based decoding architecture for low density parity check codes. CICC 2005: 703-706 - [c51]Hyeong-Ju Kang, Yongwoo Choi, Kimo Kim, In-Cheol Park, Jung-Wook Kim, Eul-Hwan Lee, Goo-Soo Gahang:
A scalable SIMD digital signal processor for high-quality multifunctional printer systems. Color Imaging: Processing, Hardcopy, and Applications 2005: 448-456 - [c50]Dong-Soo Lee, In-Cheol Park:
Low-power log-MAP turbo decoding based on reduced metric memory access. ISCAS (4) 2005: 3167-3170 - [c49]In-Cheol Park, Se-Hyeon Kang:
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation. ISCAS (6) 2005: 5778-5781 - 2004
- [c48]Young-Don Bae, In-Cheol Park:
A 4.75GOPS single-chip programmable processor array consisting of a multithreaded processor and multiple SIMD and IO processors. CICC 2004: 583-586 - [c47]Hyun-Yong Lee, In-Cheol Park:
A fast Reed-Solomon Product-Code decoder without redundant computations. ISCAS (2) 2004: 381-384 - [c46]Se-Hyeon Kang, In-Cheol Park:
Memory-based low density parity check code decoder architecture using loosely coupled two data-flows. ISCAS (2) 2004: 397-400 - [c45]Sung-Won Lee, In-Cheol Park:
Quadrature direct digital frequency synthesis using fine-grain angle rotation. ISCAS (2) 2004: 709-712 - 2003
- [j18]Myoung-Cheol Shin, In-Cheol Park:
Processor-based turbo interleaver for multiple third-generation wireless standards. IEEE Commun. Lett. 7(5): 210-212 (2003) - [j17]Young-Don Bae, Seong-Il Park, In-Cheol Park:
A single-chip programmable platform based on a multithreaded processor and configurable logic clusters. IEEE J. Solid State Circuits 38(10): 1703-1711 (2003) - [j16]Jong-Yeol Lee, In-Cheol Park:
Timed compiled-code functional simulation of embedded software for performance analysis of SOC design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 1-14 (2003) - [j15]Sung-Won Lee, In-Cheol Park:
A low-power variable length decoder for MPEG-2 based on successive decoding of short codewords. IEEE Trans. Circuits Syst. II Express Briefs 50(2): 73-82 (2003) - [j14]Seong-Il Park, Yongseok Yi, In-Cheol Park:
High performance memory mode control for HDTV decoders. IEEE Trans. Consumer Electron. 49(4): 1348-1353 (2003) - [j13]Jong-Yeol Lee, In-Cheol Park:
Address code generation for DSP instruction-set architectures. ACM Trans. Design Autom. Electr. Syst. 8(3): 384-395 (2003) - [c44]Hyeong-Ju Kang, In-Cheol Park:
SAT-based unbounded symbolic model checking. DAC 2003: 840-843 - [c43]Sung-Won Lee, In-Cheol Park:
Low-power hybrid structure of digital matched filters for direct sequence spread spectrum systems. ICASSP (2) 2003: 685-688 - [c42]In-Cheol Park, Se-Hyeon Kang, Yongseok Yi:
Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation. ICCAD 2003: 138-141 - [c41]Sung-Won Lee, In-Cheol Park:
Low-power hybrid structure of digital matched filters for direct sequence spread spectrum systems. ICME 2003: 849-852 - [c40]Sang-Chul Moon, In-Cheol Park:
Area-efficient memory-based architecture for FFT processing. ISCAS (5) 2003: 101-104 - [c39]Seong-Il Park, In-Cheol Park:
History-based memory mode prediction for improving memory performance. ISCAS (5) 2003: 185-188 - [c38]Hyeong-Ju Kang, In-Cheol Park:
Pairing and ordering to reduce hardware complexity in cascade form filter design. ISCAS (4) 2003: 265-268 - [c37]Sung-Won Lee, Hyeong-Ju Kang, In-Cheol Park:
A 24-bit floating-point audio DSP controller supporting fast exponentiation. ISCAS (2) 2003: 748-751 - [c36]Hyung Ki Ahn, In-Cheol Park, Beomsup Kim:
A 5-GHz self-calibrated I/Q clock generator using a quadrature LC-VCO. ISCAS (1) 2003: 797-800 - [c35]Jae Hoon Shim, In-Cheol Park, Beomsup Kim:
A hybrid delta-sigma modulator with adaptive calibration. ISCAS (1) 2003: 1025-1028 - 2002
- [j12]Jong-Yeol Lee, In-Cheol Park:
Loop and Address Code Optimization for Digital Signal Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(6): 1408-1415 (2002) - [j11]Chang-Jae Park, Ando Ki, In-Cheol Park, Chong-Min Kyung:
An Automatic Interface Insertion Scheme for In-System Verification of Algorithm Models in C. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2645-2654 (2002) - [j10]Seungjong Lee, Ando Ki, In-Cheol Park, Chong-Min Kyung:
Interface synthesis between software chip model and target board. J. Syst. Archit. 48(1-3): 49-57 (2002) - [j9]In-Cheol Park, Hyeong-Ju Kang:
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1525-1529 (2002) - [c34]Jong-Yeol Lee, In-Cheol Park:
Timed compiled-code simulation of embedded software for performance analysis of SOC design. DAC 2002: 293-298 - [c33]Hyeong-Ju Kang, In-Cheol Park:
A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure. ICASSP 2002: 3180-3183 - [c32]Myoung-Cheol Shin, Seong-Il Park, Sung-Won Lee, Se-Hyeon Kang, In-Cheol Park:
Area-efficient digital baseband module for Bluetooth wireless communications. ISCAS (5) 2002: 729-732 - [c31]Sung-Won Lee, In-Cheol Park:
Low cost floating-point unit design for audio applications. ISCAS (1) 2002: 869-872 - 2001
- [j8]Yongseok Yi, In-Cheol Park:
A fixed-point MPEG audio processor operating at low frequency. IEEE Trans. Consumer Electron. 47(4): 779-786 (2001) - [j7]Hansoo Kim, In-Cheol Park:
High-performance and low-power memory-interface architecture for video processing applications. IEEE Trans. Circuits Syst. Video Technol. 11(11): 1160-1170 (2001) - [c30]Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung:
Low-power high-level synthesis using latches. ASP-DAC 2001: 462-466 - [c29]In-Cheol Park, Hyeong-Ju Kang:
Digital Filter Synthesis Based on Minimal Signed Digit Representation. DAC 2001: 468-473 - [c28]Myoung-Cheol Shin, Se-Hyeon Kang, In-Cheol Park:
An Area-Efficient Iterative Modified-Booth Multiplier Based on Self-Timed Clocking. ICCD 2001: 511-512 - [c27]Jong-Yeol Lee, In-Cheol Park:
Global variable localization and transformation for hardware synthesis from high-level programming language description. ISCAS (5) 2001: 13-16 - [c26]Sung-Won Lee, In-Cheol Park:
A low-power variable length decoder based on successive decoding of shoft codewords. ISCAS (4) 2001: 582-585 - [c25]Hyeong-Ju Kang, In-Cheol Park:
Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders. ISCAS (2) 2001: 693-696 - 2000
- [j6]Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Joon Nam, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Chan-Soo Hwang, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung:
MetaCore: an application-specific programmable DSP development system. IEEE Trans. Very Large Scale Integr. Syst. 8(2): 173-183 (2000) - [c24]Young-Su Kwon, In-Cheol Park, Chong-Min Kyung:
A hardware accelerator for the specular intensity of phong illumination model in 3-dimensional graphics. ASP-DAC 2000: 559-564 - [c23]Hansoo Kim, Woo-Seung Yang, Myoung-Cheol Shin, Seung-Jai Min, Seong-Ok Bae, In-Cheol Park:
Multi-thread VLIW processor architecture for HDTV decoding. CICC 2000: 559-562 - [c22]Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park:
FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. ICCAD 2000: 51-54 - [c21]Bong-Il Park, Hoon Choi, In-Cheol Park, Chong-Min Kyung:
Synthesis and Optimization of Interface Hardware between IP's Operating at Different Clock Frequencies. ICCD 2000: 519-524 - [c20]Young-Su Kwon, In-Cheol Park, Chong-Min Kyung:
Pyramid Texture Compression and Decompression Using Interpolative Vector Quantization. ICIP 2000: 191-194 - [c19]Hansoo Kim, In-Cheol Park:
Array address translation for SDRAM-based video processing applications. VCIP 2000: 922-931 - [c18]Myoung-Cheol Shin, In-Cheol Park:
Optimal down-conversion in compressed DCT domain with minimal operations. VCIP 2000: 1613-1620
1990 – 1999
- 1999
- [j5]Seunjeogn Lee, In-Cheol Park, Chong-Min Kyung:
Path-based branch prediction using signature analysis. Microprocess. Microsystems 23(8-9): 527-536 (1999) - [j4]Hoon Choi, Jong-Sun Kim, Chi-Won Yoon, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung:
Synthesis of Application Specific Instructions for Embedded DSP Software. IEEE Trans. Computers 48(6): 603-614 (1999) - [c17]Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung:
A New Single-Clock Flip-Clop for Half-Swing Clocking. ASP-DAC 1999: 117-120 - [c16]Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung:
Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods. ASP-DAC 1999: 157-160 - [c15]You-Sung Chang, Seungjong Lee, In-Cheol Park, Chong-Min Kyung:
Verification of a Microprocessor Using Real World Applications. DAC 1999: 181-184 - [c14]Hoon Choi, Ju Hwan Yi, Jong-Yeol Lee, In-Cheol Park, Chong-Min Kyung:
Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software. DAC 1999: 939-944 - [c13]You-Sung Chang, Bong-Il Park, In-Cheol Park, Chong-Min Kyung:
Customization of a CISC Processor Core for Low-Power Applications. ICCD 1999: 152- - [c12]Bong-Il Park, In-Cheol Park, Chong-Min Kyung:
A Regular Layout Structured Multiplier Based on Weighted Carry-Save Adders. ICCD 1999: 243- - 1998
- [c11]Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung:
Virtual Chip: Making Functional Models Work on Real Target Systems. DAC 1998: 170-173 - [c10]Jin-Hyuk Yang, Byoung-Woon Kim, Sang-Jun Nam, Jang-Ho Cho, Sung-Won Seo, Chang-Ho Ryu, Young-Su Kwon, Dae-Hyun Lee, Jong-Yeol Lee, Jong-Sun Kim, Hyun-Dhong Yoon, Jae-Yeol Kim, Kun-Moo Lee, Chan-Soo Hwang, In-Hyung Kim, Jun Sung Kim, Kwang-Il Park, Kyu Ho Park, Yong Hoon Lee, Seung Ho Hwang, In-Cheol Park, Chong-Min Kyung:
MetaCore: An Application Specific DSP Development System. DAC 1998: 800-803 - [c9]Ju Hwan Yi, Hoon Choi, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung:
Multiple Behavior Module Synthesis Based on Selective Groupings. DATE 1998: 384-388 - [c8]Hoon Choi, Seung Ho Hwang, Chong-Min Kyung, In-Cheol Park:
Synthesis of application specific instructions for embedded DSP software. ICCAD 1998: 665-671 - 1997
- [j3]Joon-Seo Yim, Chang-Jae Park, In-Cheol Park, Chong-Min Kyung:
Design Verification of Complex Microprocessors. J. Circuits Syst. Comput. 7(4): 301-318 (1997) - [c7]Joon-Seo Yim, Chang-Jae Park, Woo-Seung Yang, Hun-Seung Oh, Hee-Choul Lee, Hoon Choi, Tae-Hoon Kim, Seungjong Lee, Nara Won, Yung-Hei Lee, In-Cheol Park, Chong-Min Kyung:
Verification methodology of compatible microprocessors. ASP-DAC 1997: 173-180 - [c6]Chong-Min Kyung, In-Cheol Park, Ho-Jun Song:
Multi-project chip activities in Korea-IDEC perspective. ASP-DAC 1997: 353-357 - [c5]Chong-Min Kyung, In-Cheol Park, Se-Kyoung Hong, K. S. Seong, B. S. Kong, Seungjong Lee, Hoon Choi, S. R. Maeng, D. T. Kim, Jong-Sun Kim, S. H. Park, Y. J. Kang:
HK386: an x86-compatible 32-bit CISC microprocessor. ASP-DAC 1997: 661-662 - [c4]Joon-Seo Yim, Hee-Choul Lee, Tae-Hoon Kim, Bong-Il Park, Chang-Jae Park, In-Cheol Park, Chong-Min Kyung:
Single cycle access cache for the misaligned data and instruction prefetch. ASP-DAC 1997: 677-678 - [c3]Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon Choi, Woo-Seung Yang, Hun-Seung Oh, In-Cheol Park, Chong-Min Kyung:
A C-Based RTL Design Verification Methodology for Complex Microprocessor. DAC 1997: 83-88 - 1994
- [j2]In-Cheol Park, Se-Kyoung Hong, Chong-Min Kyung:
Two Complementary Approaches for Microcode Bit Optimization. IEEE Trans. Computers 43(2): 234-239 (1994) - 1993
- [j1]In-Cheol Park, Chong-Min Kyung:
FAMOS: an efficient scheduling algorithm for high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(10): 1437-1448 (1993) - 1991
- [c2]In-Cheol Park, Chong-Min Kyung:
Fast and Near Optimal Scheduling in Automatic Data Path Aynthesis. DAC 1991: 680-685 - 1990
- [c1]Se-Kyoung Hong, In-Cheol Park, Chong-Min Kyung:
An O(n3logn)-Heuristic for Microcode Bit Optimization. ICCAD 1990: 180-183
Coauthor Index
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