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ORCIDNuno Lourenço 0003
Nuno C. Lourenço – Nuno Calado Correia Lourenço
Person information
- affiliation: University of Lisbon, Portugal
Other persons with the same name
- Nuno Lourenço 0001 — Instituto de Telecomunicações, Aveiro, Portugal
- Nuno Lourenço 0002
![[0000-0002-2154-0642]](https://dblp.org/img/orcid-mark.12x12.png "0000-0002-2154-0642")
— University of Coimbra, Portugal (and 1 more)
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2020 – today
- 2024
[j29]Gustavo Liñán Cembrano, Nuno Lourenço, Nuno Horta, José M. de la Rosa:
Design Automation of Analog and Mixed-Signal Circuits Using Neural Networks - A Tutorial Brief. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1677-1682 (2024)- 2023
- [j28]Rafael Vieira, Fábio Passos, Ricardo Martins, Nuno Horta, Nuno Lourenço:
Behavioral Analysis of Noise and Bandwidth Specifications of Heartbeat Detection Circuits for Ultra Low Power Devices. IEEE Access 11: 27330-27341 (2023) - [j27]Ricardo M. F. Martins, Nuno Lourenço:
Analog Integrated Circuit Routing Techniques: An Extensive Review. IEEE Access 11: 35965-35983 (2023) - [c48]Fábio Passos, Nuno Lourenço, Luís Mendes, Ricardo Martins, João Caldinhas Vaz, Nuno Horta:
Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models. ASP-DAC 2023: 64-69 - [c47]André Amaral, António Gusmão, Rafael Vieira, Ricardo Martins, Nuno Horta, Nuno Lourenço:
An ANN-Based Approach to the Modelling and Simulation of Analogue Circuits. SMACD 2023: 1-4 - [c46]Fábio Passos, Nuno Lourenço, Luís Mendes, Ricardo Martins, João Caldinhas Vaz, Nuno Horta:
A 23.5-32.5GHz, 17dBm PSAT and 37.5% PAE Power Amplifier Synthesized Using an Automated Design Methodology. SMACD 2023: 1-4 - [c45]Rafael Vieira, Ricardo Martins, Nuno Horta, Nuno Lourenço:
Design Space Exploration of Single-Stage OTAs towards an Ultra-Low-Power LNA for ECG Signals. SMACD 2023: 1-4 - 2022
- [j26]António Gusmão, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins:
DeepPlacer: A custom integrated OpAmp placement tool using deep models. Appl. Soft Comput. 115: 108188 (2022) - [j25]António Paiva Lapas de Gusmão, Nuno Cavaco Gomes Horta, Nuno Calado Correia Lourenço, Ricardo Miguel Ferreira Martins:
Scalable and order invariant analog integrated circuit placement with Attention-based Graph-to-Sequence deep models. Expert Syst. Appl. 207: 117954 (2022) - [c44]Fábio Passos, Rafael Vieira, António Canelas, Ricardo Póvoa, Nuno Lourenço, Nuno Horta, Jorge Guilherme:
A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/°C Stability for Space Applications. ISCAS 2022: 1-5 - [c43]Pedro Vaz, António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins:
Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator based on ANNs. ISCAS 2022: 1570-1574 - [c42]Luís Mendes, João Caldinhas Vaz, Fábio Passos, Nuno Lourenço, Ricardo Martins:
Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS. ISCAS 2022: 1988-1992 - [c41]Nuno Lourenço, Fábio Passos, Rafael Vieira, Ricardo Martins, Nuno Horta, Jorge Guilherme, Ricardo Póvoa:
Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/°C Temperature Coefficient. SMACD 2022: 1-4 - [c40]Pedro Alves, António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins:
ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage. SMACD 2022: 1-4 - [c39]João Domingues, António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins:
Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors. SMACD 2022: 1-4 - [c38]Fábio Passos, Nuno C. Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Machine Learning Approaches for Transformer Modeling. SMACD 2022: 1-4 - [c37]Rafael Vieira, Fábio Passos, Ricardo Povoa, Ricardo Martins, Nuno Horta, Jorge Guilherme, Nuno Lourenço:
Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling. SMACD 2022: 1-4 - 2021
- [j24]Luís Mendes, João Caldinhas Vaz, Fábio Passos, Nuno Lourenço, Ricardo Martins:
In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization. IEEE Access 9: 70353-70368 (2021) - [j23]António Canelas, Fábio Passos, Nuno Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs. IEEE Access 9: 124152-124164 (2021) - [j22]Ricardo Martins, Nuno Lourenço, Ricardo Póvoa, Nuno Horta:
Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing. Eng. Appl. Artif. Intell. 98: 104102 (2021) - [j21]Engin Afacan, Nuno Lourenço, Ricardo Martins, Günhan Dündar:
Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test. Integr. 77: 113-130 (2021) - [c36]António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins:
Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement. DAC 2021: 1360-1361 - 2020
- [b1]António Gusmão, Nuno Horta, Nuno Lourenço, Ricardo Martins:
Analog IC Placement Generation via Neural Networks from Unlabeled Data. Springer 2020, ISBN 978-3-030-50060-3, pp. 1-84 - [j20]Fábio Passos, Elisenda Roca, Ricardo Martins, Nuno Lourenço, Saiyd Ahyoune, Javier J. Sieiro, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology. IEEE Access 8: 51601-51609 (2020) - [j19]Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes:
A new family of CMOS inverter-based OTAs for biomedical and healthcare applications. Integr. 71: 38-48 (2020) - [j18]Ricardo Póvoa, Richa Arya, António Canelas, Fábio Passos, Ricardo Martins, Nuno Lourenço, Nuno Horta:
Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications. Microelectron. J. 95 (2020) - [j17]António Canelas, Ricardo Póvoa, Ricardo Martins, Nuno Lourenço, Jorge Guilherme, João Paulo Carvalho, Nuno Horta:
FUZYE: A Fuzzy c-Means Analog IC Yield Optimization Using Evolutionary-Based Algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 1-13 (2020) - [j16]Ricardo Póvoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes:
A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(2): 230-234 (2020) - [j15]Ricardo Martins, Nuno Lourenço, Nuno Horta, Shenke Zhong, Jun Yin, Pui-In Mak, Rui Paulo Martins:
Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools. IEEE Trans. Circuits Syst. 67-I(11): 3965-3977 (2020) - [c35]António Gusmão, Fábio Passos, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins:
Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender. ISCAS 2020: 1-5
2010 – 2019
- 2019
- [j14]Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta:
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 989-1002 (2019) - [j13]Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins:
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 69-82 (2019) - [c34]Daniel Guerra, António Canelas, Ricardo Póvoa, Nuno Horta, Nuno Lourenço, Ricardo Martins:
Artificial Neural Networks as an Alternative for Automatic Analog IC Placement. SMACD 2019: 1-4 - [c33]Nuno Lourenço, Engin Afacan, Ricardo Martins, Fábio Passos, António Canelas, Ricardo Póvoa, Nuno Horta, Günhan Dündar:
Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing. SMACD 2019: 13-16 - [c32]Ricardo Martins, Nuno Lourenço, Ricardo Póvoa, Nuno Horta:
On the Exploration of Design Tradeoffs in Analog IC Placement with Layout-dependent Effects. SMACD 2019: 25-28 - [c31]Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins:
Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm. SMACD 2019: 37-40 - [c30]Ricardo Póvoa, António Canelas, Ricardo Martins, Nuno Horta, Nuno Lourenço, João Goes:
A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers. SMACD 2019: 161-164 - [c29]Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Póvoa, Nuno Horta, Emmanuel Moutaye:
Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization. SMACD 2019: 285-288 - 2018
- [j12]Fábio Passos, Ricardo Martins, Nuno Lourenço, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández:
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology. Integr. 63: 351-361 (2018) - [j11]Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Cavaco Gomes Horta, João Goes:
Single-Stage Amplifier Biased by Voltage Combiners With Gain and Energy-Efficiency Enhancement. IEEE Trans. Circuits Syst. II Express Briefs 65-II(3): 266-270 (2018) - [j10]Ricardo Povoa, Nuno Lourenço, Ricardo Martins, António Canelas, Nuno Horta, João Goes:
Single-Stage OTA Biased by Voltage-Combiners With Enhanced Performance Using Current Starving. IEEE Trans. Circuits Syst. II Express Briefs 65-II(11): 1599-1603 (2018) - [c28]Tiago Pessoa, Nuno Lourenço, Ricardo Martins, Ricardo Povoa, Nuno Horta:
Enhanced analog and RF IC sizing methodology using PCA and NSGA-II optimization kernel. DATE 2018: 660-665 - [c27]António Canelas, Ricardo Povoa, Ricardo M. F. Martins, Nuno Lourenço, Jorge Guilherme, Nuno Horta:
A 20 DB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications. SMACD 2018: 1-4 - [c26]Fábio Passos, Ricardo Martins, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández:
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs. SMACD 2018: 1-164 - [c25]Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins:
Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications. SMACD 2018: 129-132 - [c24]Nuno Lourenço, Joao Rosa, Ricardo Martins, Helena Aidos, António Canelas, Ricardo Povoa, Nuno Horta:
On the Exploration of Promising Analog IC Designs via Artificial Neural Networks. SMACD 2018: 133-136 - 2017
- [j9]Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta:
Stochastic-based placement template generator for analog IC layout-aware synthesis. Integr. 58: 485-495 (2017) - [c23]António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta:
Efficient yield optimization method using a variable K-Means algorithm for analog IC sizing. DATE 2017: 1201-1206 - [c22]Jose Cachaco, Nuno Machado, Nuno Lourenço, Jorge Guilherme, Nuno Horta:
Automatic technology migration of analog IC designs using generic cell libraries. DATE 2017: 1281-1284 - [c21]Nuno C. Lourenço, Ricardo Martins, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization. SMACD 2017: 1-4 - [c20]Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández:
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks. SMACD 2017: 1-4 - [c19]Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno C. G. Horta:
Systematic design of a voltage controlled oscillator using a layout-aware approach. SMACD 2017: 1-4 - 2016
- [j8]Ricardo Povoa, Ivan Bastos, Nuno Lourenço, Nuno Horta:
Automatic synthesis of RF front-end blocks using multi-objective evolutionary techniques. Integr. 52: 243-252 (2016) - [j7]Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta:
Current-flow and current-density-aware multi-objective optimization of analog IC placement. Integr. 55: 295-306 (2016) - [j6]Nuno Lourenço, Ricardo Martins, António Canelas, Ricardo Povoa, Nuno Horta:
AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation. Integr. 55: 316-329 (2016) - [j5]Mrinalinee Pandey, António Canelas, Ricardo Póvoa, Jorge Alves Torres, João Costa Freire, Nuno Lourenço, Nuno Horta:
Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer. Integr. 55: 330-340 (2016) - [c18]David Neves, Ricardo Martins, Nuno Lourenço, Nuno Horta:
Design automation tasks scheduling for enhanced parallel execution of a state-of-the-art layout-aware sizing approach. DATE 2016: 1513-1516 - [c17]Ricardo Martins, António Canelas, Nuno Lourenço, Nuno Horta:
On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies. SMACD 2016: 1-4 - [c16]António Canelas, Ricardo Martins, Ricardo Povoa, Nuno Lourenço, Nuno Horta:
Yield optimization using k-means clustering algorithm to reduce Monte Carlo simulations. SMACD 2016: 1-4 - [c15]Andre Ferreira, Nuno Lourenço, Ricardo Martins, Nuno Horta:
Automated analog IC design constraints generation for a layout-aware sizing approach. SMACD 2016: 1-4 - 2015
- [j4]Ricardo Martins, Nuno Lourenço, Nuno Horta:
Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates. Expert Syst. Appl. 42(23): 9137-9151 (2015) - [j3]Nuno Lourenço, António Canelas, Ricardo Povoa, Ricardo Martins, Nuno Horta:
Floorplan-aware analog IC sizing and optimization based on topological constraints. Integr. 48: 183-197 (2015) - [c14]Nuno Lourenço, Ricardo Martins, Nuno Horta:
Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction. DATE 2015: 1156-1161 - [c13]Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta:
Extraction and application of wiring symmetry rules to route analog multiport terminals. ISCAS 2015: 1945-1948 - [c12]Ricardo Povoa, Nuno Lourenço, Nuno Horta, João Goes:
A voltage-combiners-biased amplifier with enhanced gain and speed using current starving. ISCAS 2015: 2069-2072 - 2014
- [j2]Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta:
Electromigration-aware analog Router with multilayer multiport terminal structures. Integr. 47(4): 532-547 (2014) - [c11]Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta:
Electromigration-aware and IR-Drop avoidance routing in analog multiport terminal structures. DATE 2014: 1-6 - [c10]Ricardo Povoa, Nuno Lourenço, Nuno Horta, Rui Santos-Tavares, João Goes:
A cascode-free single-stage amplifier using a fully-differential folded voltage-combiner. ICECS 2014: 263-266 - [c9]Ricardo Povoa, Ricardo Lourenco, Nuno Lourenço, António Canelas, Ricardo Martins, Nuno Horta:
LC-VCO automatic synthesis using multi-objective evolutionary techniques. ISCAS 2014: 293-296 - 2013
- [j1]Ricardo Martins, Nuno Lourenço, Nuno Horta:
LAYGEN II - Automatic Layout Generation of Analog Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1641-1654 (2013) - [c8]Frederico Rocha, Nuno Lourenço, Ricardo Povoa, Ricardo Martins, Nuno Horta:
A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis. IEEE Congress on Evolutionary Computation 2013: 2781-2788 - [c7]Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta:
Multi-port multi-terminal analog router based on an evolutionary optimization kernel. IEEE Congress on Evolutionary Computation 2013: 2789-2796 - [c6]Frederico Rocha, Ricardo Martins, Nuno Lourenço, Nuno Horta:
Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel. DoCEIS 2013: 531-538 - [c5]Ricardo Povoa, Nuno Lourenço, Nuno Horta, Rui Santos-Tavares, João Goes:
Single-stage amplifiers with gain enhancement and improved energy-efficiency employing voltage-combiners. VLSI-SoC 2013: 19-22 - 2012
- [c4]Nuno Lourenço, Nuno Horta:
GENOM-POF: multi-objective evolutionary synthesis of analog ICs with corners validation. GECCO 2012: 1119-1126 - [c3]Ricardo Martins, Nuno Lourenço, Nuno Horta:
LAYGEN II: automatic analog ICs layout generator based on a template approach. GECCO 2012: 1127-1134
2000 – 2009
- 2007
- [c2]Nuno C. Lourenço, Nuno C. G. Horta:
Automatic analog IC layout generation based on a evolutionary computation approach. GECCO 2007: 2261 - 2005
- [c1]Nuno Lourenço, Nuno Horta:
Laygen - An evolutionary approach to automatic analog IC layout generation. ICECS 2005: 1-4
Coauthor Index
António Gusmão 0001
aka: António Paiva Lapas de Gusmão
aka: António Paiva Lapas de Gusmão
[j29] [j28] [c48] [c47] [c46] [c45] [j26] [j25] [c44] [c43] [c41] [c40] [c39] [c38] [c37] [j23] [j22] [c36] [b1] [j20] [j19] [j18] [j17] [j16] [j15] [c35] [j14] [j13] [c34] [c33] [c32] [c31] [c30] [c29] [j12] [j11] [j10] [c28] [c27] [c26] [c25] [c24] [j9] [c23] [c22] [c21] [c20] [c19] [j8] [j7] [j6] [j5] [c18] [c17] [c16] [c15] [j4] [j3] [c14] [c13] [c12] [j2] [c11] [c10] [c9] [j1] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
[j28] [j27] [c48] [c47] [c46] [c45] [j26] [j25] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [j24] [j23] [j22] [j21] [c36] [b1] [j20] [j19] [j18] [j17] [j16] [j15] [c35] [j14] [j13] [c34] [c33] [c32] [c31] [c30] [c29] [j12] [j11] [j10] [c28] [c27] [c26] [c25] [c24] [j9] [c23] [c21] [c20] [c19] [j7] [j6] [c18] [c17] [c16] [c15] [j4] [j3] [c14] [c13] [j2] [c11] [c9] [j1] [c8] [c7] [c6] [c3]
Ricardo Povoa
aka: Ricardo Póvoa
aka: Ricardo Póvoa
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