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ORCIDReiner Kolla
Person information
- affiliation: University of Würzburg, Germany
- affiliation: Saarland University, Saarbrücken, Germany
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2010 – 2019
- 2017
[j10]Armin Runge
, Reiner Kolla:
TwoPhases: A transmission scheme to reduce the link width at deflection routing based Network-on-Chips. J. Syst. Archit. 75: 145-154 (2017)- [c25]Isabel Madeleine Runge, Reiner Kolla:
MCGC: A Network Coding Approach for Reliable Large-scale Wireless Networks. FAILSAFE@SenSys 2017: 16-23 - 2016
- [c24]Armin Runge, Reiner Kolla:
An Alternating Transmission Scheme for Deflection Routing Based Network-on-Chips. ARCS 2016: 48-59 - [c23]Aulia Arif Iskandar, Reiner Kolla, Klaus Schilling, Wolfram Völker:
A wearable 1-lead necklace ECG for continuous heart rate monitoring. HealthCom 2016: 1-4 - [c22]Armin Runge, Reiner Kolla:
Consideration of the Flit Size for Deflection Routing based Network-on-Chips. AISTECS@HiPEAC 2016: 5:1-5:6 - [c21]Armin Runge, Reiner Kolla:
Using benes networks at fault-tolerant and deflection routing based network-on-chips. NOCS 2016: 1-8 - 2011
- [c20]Armin Runge, Marcel Baunach, Reiner Kolla:
Precise self-calibration of ultrasound based indoor localization systems. IPIN 2011: 1-8
2000 – 2009
- 2007
- [c19]Marcel Baunach, Reiner Kolla, Clemens Muhlberger:
A Method for Self-Organizing Communication in WSN Based Localization Systems: HashSlot. LCN 2007: 825-832 - [c18]Marcel Baunach, Reiner Kolla, Clemens Muhlberger:
Beyond Theory: Development of a Real World Localization Application as Low Power WSN. LCN 2007: 872-884 - 2003
- [j9]Frank Wolz, Reiner Kolla:
Disproving the Perfect-Rate Property of Data-Flow Graphs Unfolded by the Least Common Multiple of the Number of Loop Registers. IEEE Trans. Computers 52(5): 688 (2003) - 2002
- [c17]Frank Wolz, Reiner Kolla:
A Retargetable Macro Generation Method for the Evaluation of Repetitive Configurable Architectures. FPL 2002: 997-1006 - 2001
- [c16]Frank Wolz, Reiner Kolla:
Bubble Partitioning for LUT-Based Sequential Circuits. FPL 2001: 336-345 - 2000
- [j8]Reiner Kolla:
Technology Binding. Inform. Spektrum 23(3): 212-215 (2000) - [c15]Frank Wolz, Reiner Kolla:
A New Floorplanning Method for FPGA Architectural Research. FPL 2000: 432-442
1990 – 1999
- 1999
- [c14]Reiner Kolla, A. Vodopivec, Jürgen Wolff von Gudenberg:
Splitting Double Precision FPUs for Single Precision Interval Arithmetic. ARCS Workshops 1999: 5-16 - [c13]Winfried Nöth, Reiner Kolla:
Spanning Tree-based State Encoding for Low Power Dissipation. DATE 1999: 168-174 - 1998
- [c12]Uwe Hinsberger, Reiner Kolla:
Boolean Matching for Large Libraries. DAC 1998: 206-211 - [c11]Reiner Kolla, Oliver Springauf:
PACE: Processor Architectures for Circuit Emulation. IPPS/SPDP Workshops 1998: 105-110 - 1997
- [c10]Uwe Hinsberger, Reiner Kolla, Markus Wild:
A parallel hybrid approach to hard optimization problems. ARCS 1997: 201-210 - [c9]Winfried Nöth, Reiner Kolla:
Node normalization and decomposition in low power technology mapping. ISLPED 1997: 275-280 - 1996
- [c8]Winfried Nöth, Uwe Hinsberger, Reiner Kolla:
TROY: A Tree-Based Approach to Logic Synthesis and Technology Mapping. Great Lakes Symposium on VLSI 1996: 188-193 - 1995
- [c7]Uwe Hinsberger, Reiner Kolla:
Optimal technology mapping for single output cells. Great Lakes Symposium on VLSI 1995: 14- - 1992
- [j7]Uwe Hinsberger, Reiner Kolla:
A cell-based approach to performance optimization of fanout-free circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(10): 1317-1322 (1992) - [p1]Uwe Hinsberger, Reiner Kolla:
Performance Optimization of Combinational Circuits. Informatik 1992: 185-208 - 1991
- [j6]Reiner Kolla, Bernd Serf:
The Virtual Feedback Problem in Hierarchical Representations of Combinational Circuits. Acta Informatica 28(5): 463-476 (1991) - 1990
- [j5]Reiner Kolla:
Minimal Area Sizing of Power Supply Nets in VLSI Circuits. J. Inf. Process. Cybern. 26(11/12): 585-605 (1990) - [c6]Bernd Becker, Thomas Burch, Günter Hotz, D. Kiel, Reiner Kolla, Paul Molitor, Hans-Georg Osthof, Gisela Pitsch, Uwe Sparmann:
A graphical system for hierarchical specifications and checkups of VLSI circuits. EURO-DAC 1990: 174-179 - [c5]Uwe Hinsberger, Reiner Kolla:
Cell based performance optimization of combinational circuits. EURO-DAC 1990: 594-599 - [c4]Reiner Kolla:
A dynamic programming approach to the power supply net sizing problem. EURO-DAC 1990: 600-604
1980 – 1989
- 1989
- [b2]Reiner Kolla, Paul Molitor, Hans-Georg Osthof:
Einführung in den VLSI-Entwurf. Leitfäden und Monographien der Informatik, Teubner 1989, ISBN 978-3-519-02273-2, pp. 1-352 - [j4]Reiner Kolla, Paul Molitor:
A note on hierarchical layer-assignment. Integr. 7(3): 213-230 (1989) - 1988
- [c3]Bernd Becker, Reiner Kolla:
On the Construction of Optimal Time Adders (Extended Abstract). STACS 1988: 18-28 - 1987
- [b1]Reiner Kolla:
Spezifikation und Expansion logisch-topologischer Netze. Saarland University, Saarbrücken, Germany, 1987, pp. 1-144 - [c2]Bernd Becker, Günter Hotz, Reiner Kolla, Paul Molitor, Hans-Georg Osthof:
Hierarchical Design Based on a Calculus of Nets. DAC 1987: 649-653 - 1986
- [j3]Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor:
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I. Inform. Forsch. Entwickl. 1(1): 38-47 (1986) - [j2]Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor:
Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II. Inform. Forsch. Entwickl. 1(2): 72-82 (1986) - [c1]Günter Hotz, Reiner Kolla, Paul Molitor:
On Network Algebras and Recursive Equations. Graph-Grammars and Their Application to Computer Science 1986: 250-261 - 1983
- [j1]Reiner Kolla:
Where-Oblivious is not Sufficient. Inf. Process. Lett. 17(5): 263-268 (1983)
Coauthor Index
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