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ORCIDJunichi Miyakoshi
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2020 – today
- 2023
[j12]Takeshi Kato
, Yasuyuki Kudo, Junichi Miyakoshi, Misa Owa, Yasuhiro Asa, Takashi Numata, Ryuji Mine, Hiroyuki Mizuno:
Social Co-OS: Cyber-human social Co-operating system. IET Cyper-Phys. Syst.: Theory & Appl. 8(1): 1-14 (2023)- [i5]Misa Owa, Junichi Miyakoshi, Takeshi Kato:
Subjective-objective policy making approach: Coupling of resident-values multiple regression analysis with value-indices, multi-agent-based simulation. CoRR abs/2306.08208 (2023) - [i4]Junichi Miyakoshi:
Modeling pattern formation in communities by using information particles. CoRR abs/2307.10270 (2023) - [i3]Takeshi Kato, Junichi Miyakoshi, Tadayuki Matsumura, Ryuji Mine, Hiroyuki Mizuno, Yasuo Deguchi:
Mixbiotic society measures: Assessment of community well-going as living system. CoRR abs/2307.11594 (2023) - [i2]Takeshi Kato, Junichi Miyakoshi, Tadayuki Matsumura, Yasuyuki Kudo, Ryuji Mine, Hiroyuki Mizuno, Yasuo Deguchi:
Mixbiotic society measures: Comparison of organizational structures based on communication simulation. CoRR abs/2307.15297 (2023) - 2021
- [i1]Takeshi Kato, Yasuyuki Kudo, Junichi Miyakoshi, Misa Owa, Yasuhiro Asa, Takashi Numata, Ryuji Mine, Hiroyuki Mizuno:
Social Co-OS: Cyber-Human Social Co-Operating System. CoRR abs/2110.01861 (2021)
2010 – 2019
- 2013
- [c11]Atsushi Miyamoto, Junichi Miyakoshi, Kazuki Matsuzaki, Toshiyuki Irie:
False-positive reduction of liver tumor detection using ensemble learning method. Image Processing 2013: 86693B - 2012
- [c10]Shuntaro Yui, Junichi Miyakoshi, Kazuki Matsuzaki, Toshiyuki Irie, Ryo Kurazume:
Size-adaptive hepatocellular carcinoma detection from 3D CT images based on the level set method. Computer-Aided Diagnosis 2012: 83151P - [c9]Junichi Miyakoshi, Shuntaro Yui, Kazuki Matsuzaki, Toshiyuki Irie:
Metastatic liver tumor detection from 3D CT images using a level set algorithm with liver-edge term. Image Processing 2012: 83142C - 2011
- [j11]Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima:
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. IEICE Trans. Electron. 94-C(4): 663-669 (2011) - 2010
- [c8]Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima:
A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC 2010: 100-101
2000 – 2009
- 2008
- [j10]Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi, Hajime Ishihara, Masayuki Miyama, Yoshio Matsuda, Masahiko Yoshimoto:
A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition. IEICE Trans. Electron. 91-C(4): 457-464 (2008) - [j9]Yuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Sub 100 mW H.264 [email protected] Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer. IEICE Trans. Electron. 91-C(4): 465-478 (2008) - [j8]Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 620-627 (2008) - [c7]Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto:
An H.264/AVC [email protected] quarter-pel motion estimation processor VLSI for real-time MBAFF encoding. ICECS 2008: 1179-1182 - [c6]Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A sub 100 mW H.264/AVC [email protected] integer-pel motion estimation processor VLSI for MBAFF encoding. ISCAS 2008: 848-851 - 2006
- [j7]Noriyuki Minegishi, Junichi Miyakoshi, Yuki Kuroda, Tadayoshi Katagiri, Yuki Fukuyama, Ryo Yamamoto, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation. IEICE Trans. Electron. 89-C(3): 230-242 (2006) - [j6]Junichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing. IEICE Trans. Electron. 89-C(11): 1629-1636 (2006) - [j5]Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto:
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3623-3633 (2006) - [j4]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3634-3641 (2006) - [c5]Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66 - [c4]Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno:
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. VLSI-SoC 2006: 192-197 - 2005
- [j3]Junichi Miyakoshi, Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto:
A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation. IEICE Trans. Electron. 88-C(4): 559-569 (2005) - [j2]Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Junichi Miyakoshi, Masayuki Miyama, Masahiko Yoshimoto:
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3492-3499 (2005) - 2004
- [j1]Masayuki Miyama, Junichi Miyakoshi, Yuki Kuroda, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application. IEEE J. Solid State Circuits 39(9): 1562-1570 (2004) - [c3]Yuki Kuroda, Junichi Miyakoshi, Masayuki Miyama, Kousuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application. ASP-DAC 2004: 527-528 - 2003
- [c2]Junichi Miyakoshi, Yuri Kuroda, Masayuki Miyama, Kosuke Imamura, Hideo Hashimoto, Masahiko Yoshimoto:
A sub-mW MPEG-4 motion estimation processor core for mobile video application. CICC 2003: 181-184 - 2002
- [c1]Masayuki Miyama, Osamu Tooyama, N. Takamatsu, T. Kodake, K. Nakamura, A. Kato, Junichi Miyakoshi, K. Hashimoto, Shigenobu Komatsu, M. Yagi, Masao Morimoto, Kazuo Taki, Masahiko Yoshimoto:
An ultra low power, realtime MPEG2 MP@HL motion estimation processor core with SIMD datapath architecture optimized for gradient descent search algorithm. CICC 2002: 167-170
Coauthor Index
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