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2020 – today
- 2020
[j7]Peng Yang
, Zhehui Wang, Zhifei Wang, Jiang Xu, Yi-Shing Chang, Xuanqi Chen, Rafael K. V. Maeda, Jun Feng:
Multidomain Inter/Intrachip Silicon Photonic Networks for Energy-Efficient Rack-Scale Computing Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 626-639 (2020)- [j6]Zhifei Wang, Peng Yang, Yi-Shing Chang, Jiang Xu, Xuanqi Chen, Zhehui Wang, Jun Feng:
A Cross-Layer Optimization Framework for Integrated Optical Switches in Data Centers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(3): 640-653 (2020) - [j5]Xuanqi Chen, Zhifei Wang, Yi-Shing Chang, Jiang Xu, Jun Feng, Peng Yang, Zhehui Wang, Luan H. K. Duong:
Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(5): 977-990 (2020) - [j4]Zhehui Wang, Zhifei Wang, Jiang Xu, Yi-Shing Chang, Jun Feng, Xuanqi Chen, Shixi Chen, Jiaxu Zhang:
CAMON: Low-Cost Silicon Photonic Chiplet for Manycore Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1820-1833 (2020)
2010 – 2019
- 2019
- [j3]Luan H. K. Duong, Peng Yang, Zhifei Wang, Yi-Shing Chang, Jiang Xu, Zhehui Wang, Xuanqi Chen:
Crosstalk Noise Reduction Through Adaptive Power Control in Inter/Intra-Chip Optical Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(1): 43-56 (2019) - 2018
- [c15]Xuanqi Chen, Zhifei Wang, Yi-Shing Chang, Jiang Xu, Peng Yang, Zhehui Wang, Luan H. K. Duong:
A Comprehensive Electro-Optical Model for Silicon Photonic Switches. ISVLSI 2018: 76-81
2000 – 2009
- 2008
- [j2]Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty:
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. J. Electron. Test. 24(1-3): 259-269 (2008) - [c14]Jian Kang, Sharad C. Seth, Yi-Shing Chang, Vijay Gangaram:
Efficient Selection of Observation Points for Functional Tests. ISQED 2008: 236-241 - [c13]I-De Huang, Yi-Shing Chang, Suriyaprakash Natarajan, Ramesh Sharma, Sandeep K. Gupta:
On Accelerating Path Delay Fault Simulation of Long Test Sequences. ITC 2008: 1-9 - [c12]I-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty:
An Industrial Case Study of Sticky Path-Delay Faults. VTS 2008: 395-402 - 2006
- [c11]Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty:
An Approach to Minimizing Functional Constraints. DFT 2006: 215-226 - [c10]Manan Syal, Kameshwar Chandrasekar, Vishnu C. Vimjam, Michael S. Hsiao, Yi-Shing Chang, Sreejit Chakravarty:
A Study of Implication Based Pseudo Functional Testing. ITC 2006: 1-10 - 2005
- [j1]Sandip Kundu, Sujit T. Zachariah, Yi-Shing Chang, Chandra Tirumurti:
On modeling crosstalk faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(12): 1909-1915 (2005) - [c9]Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee:
Transition Tests for High Performance Microprocessors. VTS 2005: 29-34 - [c8]Sreejit Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee:
Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor. VTS 2005: 337-342 - 2004
- [c7]Chandra Tirumurti, Sandip Kundu, Susmita Sur-Kolay, Yi-Shing Chang:
A Modeling Approach for Addressing Power Supply Switching Noise Related Failures of Integrated Circuit. DATE 2004: 1078-1083 - 2003
- [c6]Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti:
On Modeling Cross-Talk Faults. DATE 2003: 10490-10495 - [c5]Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Maximizing Ground Bounce Considering Circuit Delay. VTS 2003: 151-157 - 2001
- [c4]Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. VTS 2001: 358-367
1990 – 1999
- 1999
- [c3]Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Test Generation for Ground Bounce in Internal Logic Circuitry. VTS 1999: 95-105 - 1997
- [c2]Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
Analysis of Ground Bounce in Deep Sub-Micron Circuits. VTS 1997: 110-116 - 1992
- [c1]Thou-Ho Chen, Liang-Gee Chen, Yi-Shing Chang:
Design of Concurrent Error-Detectable VLSI-Based Array Dividers. ICCD 1992: 72-75
Coauthor Index
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