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ORCIDJan Kastil
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2010 – 2019
- 2016
[b1]Jan Kastil:
Optimalizace algoritmů a DatovýCH Struktur Pro VyhledáVání ReguláRníCH VýRazů S VyužITíM Technologie FPGA ; Optimization of Algorithms and Data Structures for Regular expression Matching using FPGA Technology. Brno University of Technology, Czech Republic, 2016- 2015
- [c15]Martin Krcma, Jan Kastil, Zdenek Kotásek:
Mapping Trained Neural Networks to FPNNs. DDECS 2015: 157-160 - [c14]Martin Krcma, Zdenek Kotásek, Jan Kastil:
Fault tolerant Field Programmable Neural Networks. NORCAS 2015: 1-4 - 2014
- [c13]Lucie Matuova, Jan Kastil
, Zdenek Kotásek:
Automatic Construction of On-line Checking Circuits Based on Finite Automata. DSD 2014: 326-332 - 2013
- [j1]Martin Straka, Jan Kastil, Zdenek Kotásek, Lukas Miculka:
Fault tolerant system design and SEU injection based testing. Microprocess. Microsystems 37(2): 155-173 (2013) - [c12]Jan Kastil, Vlastimil Kosar, Jan Korenek:
Hardware architecture for the fast pattern matching. DDECS 2013: 120-123 - [c11]Karel Szurman, Jan Kastil, Martin Straka, Zdenek Kotásek:
Fault tolerant CAN bus control system implemented into FPGA. DDECS 2013: 289-292 - 2012
- [c10]Martin Straka, Lukas Miculka, Jan Kastil, Zdenek Kotásek:
Test platform for fault tolerant systems design properties verification. DDECS 2012: 336-341 - [c9]Jan Kastil, Martin Straka, Lukas Miculka, Zdenek Kotásek:
Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. DSD 2012: 250-257 - 2011
- [c8]Viktor Pus, Jiri Tobola, Vlastimil Kosar, Jan Kastil, Jan Korenek:
Netbench: Framework for Evaluation of Packet Processing Algorithms. ANCS 2011: 95-96 - [c7]Martin Straka, Jan Kastil, Jaroslav Novotný, Zdenek Kotásek:
Advanced fault tolerant bus for multicore system implemented in FPGA. DDECS 2011: 397-398 - [c6]Martin Straka, Jan Kastil, Zdenek Kotásek:
SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems. DSD 2011: 223-230 - 2010
- [c5]Jan Kastil, Jan Korenek:
High speed pattern matching algorithm based on deterministic finite automata with faulty transition table. ANCS 2010: 7 - [c4]Jan Kastil, Jan Korenek:
Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashing. DDECS 2010: 149-152 - [c3]Martin Straka, Jan Kastil, Zdenek Kotásek:
Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs. DDECS 2010: 173-176 - [c2]Martin Straka, Jan Kastil, Zdenek Kotásek:
Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration. DSD 2010: 365-372
2000 – 2009
- 2009
- [c1]Jan Kastil, Jan Korenek, Ondrej Lengál:
Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing. DSD 2009: 823-829
Coauthor Index
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