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ORCIDSrinivas Patil
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2010 – 2019
- 2012
[j9]Hongxia Fang, Krishnendu Chakrabarty
, Abhijit Jas, Srinivas Patil, Chandra Tirumurti:
Functional Test-Sequence Grading at Register-Transfer Level. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1890-1894 (2012)- [c21]Naghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil:
Test generation for clock-domain crossing faults in integrated circuits. DATE 2012: 406-411 - 2011
- [c20]Naghmeh Karimi, Zhiqiu Kong, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil:
Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip. Asian Test Symposium 2011: 7-14
2000 – 2009
- 2009
- [j8]Gadi Singer, Rajesh Galivanche, Srinivas Patil, Mike Tripp:
The Challenges of Nanotechnology and Gigacomplexity. IEEE Des. Test Comput. 26(1): 88-93 (2009) - [j7]Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas:
FPGA-based hardware acceleration for Boolean satisfiability. ACM Trans. Design Autom. Electr. Syst. 14(2): 33:1-33:11 (2009) - [c19]Hongxia Fang, Krishnendu Chakrabarty, Abhijit Jas, Srinivas Patil, Chandra Tirumurti:
RT-Level Deviation-Based Grading of Functional Test Sequences. VTS 2009: 264-269 - 2008
- [c18]Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche:
A low-cost concurrent error detection technique for processor control logic. DATE 2008: 897-902 - 2007
- [c17]Abhijit Jas, Suriyaprakash Natarajan, Srinivas Patil:
The Region-Exhaustive Fault Model. ATS 2007: 13-18 - [c16]Irith Pomeranz, Praveen Parvathala, Srinivas Patil:
Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation. ATS 2007: 25-32 - [c15]Abhijit Jas, Srinivas Patil:
Analysis of Specified Bit Handling Capability of Combinational Expander Networks. DFT 2007: 252-260 - 2006
- [c14]Irith Pomeranz, Srinivas Patil, Praveen Parvathala:
A Functional Fault Model with Implicit Fault Effect Propagation Requirements. ATS 2006: 95-102 - [c13]Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz:
Selecting High-Quality Delay Tests for Manufacturing Test and Debug. DFT 2006: 59-70 - [c12]Sungchul Park, Li Chen, Praveen Parvathala, Srinivas Patil, Irith Pomeranz:
A Functional Coverage Metric for Estimating the Gate-Level Fault Coverage of Functional Tests. ITC 2006: 1-10 - [c11]Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty:
Path Delay Fault Simulation on Large Industrial Designs. VTS 2006: 16-23 - 2005
- [c10]Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas Patil:
Compressing Functional Tests for Microprocessors. Asian Test Symposium 2005: 428-433
1990 – 1999
- 1996
- [j6]Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams:
A weighted random pattern test generation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8): 1020-1025 (1996) - 1994
- [j5]Jacob Savir, Srinivas Patil:
Broad-side delay test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8): 1057-1064 (1994) - [j4]Jacob Savir, Srinivas Patil:
On broad-side delay test. IEEE Trans. Very Large Scale Integr. Syst. 2(3): 368-372 (1994) - [c9]Rohit Kapur, Srinivas Patil, Thomas J. Snethen, Thomas W. Williams:
Design of an Efficient Weighted-Random-Pattern Generation System. ITC 1994: 491-500 - [c8]Jacob Savir, Srinivas Patil:
On broad-side delay test. VTS 1994: 284-290 - 1993
- [j3]Jacob Savir, Srinivas Patil:
Scan-based transition test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8): 1232-1241 (1993) - 1992
- [c7]Srinivas Patil, Jacob Savir:
Skewed-Load Transition Test: Part 2, Coverage. ITC 1992: 714-722 - 1991
- [b1]Srinivas Patil:
Parallel algorithms for test generation and fault simulation. University of Illinois Urbana-Champaign, USA, 1991 - [j2]Srinivas Patil, Prithviraj Banerjee:
Performance trade-offs in a parallel test generation/fault simulation environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(12): 1542-1558 (1991) - [c6]Srinivas Patil, Prithviraj Banerjee, Janak H. Patel:
Parallel Test Generation for Sequential Circuits on General-Purpose Multiprocessors. DAC 1991: 155-159 - [c5]Sungho Kim, Prithviraj Banerjee, Srinivas Patil:
A Layout Driven Design for Testability Technique for MOS VLSI Circuits. ITC 1991: 157-165 - 1990
- [j1]Srinivas Patil, Prithviraj Banerjee:
A parallel branch and bound algorithm for test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 313-322 (1990)
1980 – 1989
- 1989
- [c4]Srinivas Patil, Prithviraj Banerjee:
A Parallel Branch and Bound Algorithm for Test Generation. DAC 1989: 339-343 - [c3]Srinivas Patil, Sudhakar M. Reddy:
A test generation system for path delay faults. ICCD 1989: 40-43 - [c2]Srinivas Patil, Prithviraj Banerjee:
Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment. ITC 1989: 718-726 - [c1]Srinivas Patil, Prithviraj Banerjee, Constantine D. Polychronopoulos:
Efficient circuit partitioning algorithms for parallel logic simulation. SC 1989: 361-370
Coauthor Index
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