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Satya K. Vendra

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2020 – today

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2021
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Sucheta Mohapatra, Satya K. Vendra, Malgorzata Chrzanowska-Jeske:
Fast Buffer Count Estimation in 3D IC Floorplanning. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 271-275 (2021)
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Satya K. Vendra, Malgorzata Chrzanowska-Jeske:
Fast Thermal Goodness Evaluation of a 3D-IC Floorplan. ISQED 2021: 367-373

2010 – 2019

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2018
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Satya K. Vendra, Malgorzata Chrzanowska-Jeske:
Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile. ISCAS 2018: 1-5

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