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2020 – today
- 2024
[j4]Viktor Razilov, Robert Wittig, Emil Matús, Gerhard P. Fettweis:
Access Interval Prediction by Partial Matching for Tightly Coupled Memory Systems. Int. J. Parallel Program. 52(1-2): 3-19 (2024)- [c20]Simon Friedrich, Robert Wittig, Emil Matús, Darius Grantz, Martin Zeller, Jens Benndorf, Gerhard P. Fettweis:
A 22 nm 10 TOPS Mixed-Precision Neural Network SoC for Image Processing with Energy-Efficient Dilated Convolution Support. COOL CHIPS 2024: 1-3 - 2023
- [c19]Fabian Kempf, Julian Höfer
, Tanja Harbaum, Jürgen Becker, Nael Fasfous, Alexander Frickenstein, Hans-Jörg Vögel, Simon Friedrich, Robert Wittig, Emil Matús, Gerhard P. Fettweis, Matthias Lüders, Holger Blume, Jens Benndorf, Darius Grantz, Martin Zeller, Dietmar Engelke, Karl-Heinz Eickel:
The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety Perspective. DATE 2023: 1-6 - [c18]Simon Friedrich, Chia-Ying Lin, Viktor Razilov, Robert Wittig, Emil Matús, Gerhard P. Fettweis:
Access Interval Prediction with Neural Networks for Tightly Coupled Memory Systems. DSD 2023: 391-398 - [c17]Simon Friedrich, Shambhavi Balamuthu Sampath, Robert Wittig, Manoj Rohit Vemparala, Nael Fasfous, Emil Matús, Walter Stechele, Gerhard P. Fettweis:
Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision Operands. ISQED 2023: 1-8 - [c16]Simon Friedrich, Thomas Nalapat, Robert Wittig, Emil Matús, Gerhard P. Fettweis:
On-Chip Memory Access Reduction for Energy-Efficient Dilated Convolution Processing. SAMOS 2023: 478-485 - 2022
- [j3]Robert Wittig, Philipp Schulz, Emil Matús, Gerhard P. Fettweis:
Accurate Estimation of Service Rates in Interleaved Scratchpad Memory Systems. ACM Trans. Embed. Comput. Syst. 21(1): 4:1-4:15 (2022) - [c15]Mattis Hasler, Sebastian Haas, Robert Wittig, Stefan Scholze, Andreas Dixius, Sebastian Höppner, Gerhard P. Fettweis, Christian Mayr:
A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI. ISVLSI 2022: 217-222 - [c14]Viktor Razilov, Robert Wittig, Emil Matús, Gerhard P. Fettweis:
Tagged Geometric History Length Access Interval Prediction for Tightly Coupled Memory Systems. SAMOS 2022: 90-100 - 2021
- [b1]Robert Wittig:
Architectures and Theoretical Models for Shared Scratchpad Memory Systems. Dresden University of Technology, Germany, 2021 - [c13]Zohra Charania, Chris Paul Iatrou, Valentin Khaydarov, Richard Jacob, Robert Wittig, Heiner Bauer, Sebastian Höppner, René Bachmann, Philipp Bauer, Hendrik Deckert, Christian Mayr, Gerhard P. Fettweis, Leon Urbas:
Opportunities For A Hardware-Based OPC UA Server Implementation In Industry 4.0. IECON 2021: 1-6 - 2020
- [j2]Mattis Hasler, Robert Wittig, Emil Matús, Gerhard P. Fettweis:
Slicing FIFOs for On-Chip Memory Bandwidth Exhaustion. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(2): 441-450 (2020) - [c12]Mattis Hasler, Robert Wittig, Emil Matús, Gerhard P. Fettweis:
Balancing Dynamic Scheduling Overhead to Maximize SDF Performance. 6G SUMMIT 2020: 1-5 - [c11]Robert Wittig, Andrés Goens, Christian Menard, Emil Matús, Gerhard P. Fettweis, Jerónimo Castrillón:
Modem Design in the Era of 5G and Beyond: The Need for a Formal Approach. ICT 2020: 1-5
2010 – 2019
- 2019
- [c10]Gerhard P. Fettweis, Mattis Hasler, Robert Wittig, Emil Matús, Stefan A. Damjancevic, Sebastian Haas, Friedrich Pauls, Seungseok Nam, Nairuhi Grigoryan:
A Low-Power Scalable Signal Processing Chip Platform for 5G and Beyond - Kachel. ACSSC 2019: 896-900 - [c9]Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis:
Statistical Access Interval Prediction for Tightly Coupled Memory Systems. COOL CHIPS 2019: 1-3 - [c8]Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis:
Queue Based Memory Management Unit for Heterogeneous MPSoCs. DATE 2019: 1297-1300 - [c7]Robert Wittig, Stefan A. Damjancevic, Emil Matús, Gerhard P. Fettweis:
General Multicarrier Modulation Hardware Accelerator for the Internet of Things. GLOBECOM 2019: 1-6 - [c6]Mattis Hasler, Robert Wittig, Emil Matús, Gerhard P. Fettweis:
A Hybrid Execution Approach to Improve the Performance of Dataflow Applications. ISOCC 2019: 107-108 - [c5]Friedrich Pauls, Robert Wittig, Gerhard P. Fettweis:
A Latency-Optimized Hash-Based Digital Signature Accelerator for the Tactile Internet. SAMOS 2019: 93-106 - [c4]Robert Wittig, Friedrich Pauls, Emil Matús, Gerhard P. Fettweis:
Access Interval Prediction for Tightly Coupled Memory Systems. SAMOS 2019: 229-240 - [c3]Gerhard P. Fettweis, Emil Matús, Robert Wittig, Mattis Hasler, Stefan A. Damjancevic, Seungseok Nam, Sebastian Haas:
5G-and-Beyond Scalable Machines. VLSI-SoC 2019: 105-109 - [c2]Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis:
Probabilistic Models for Off-Line Arbiters in Embedded Systems. VLSI-SoC 2019: 238-239 - 2018
- [j1]Jens Müller, Robert Wittig, Jan Müller, Ronald Tetzlaff:
An Improved Cellular Nonlinear Network Architecture for Binary and Grayscale Image Processing. IEEE Trans. Circuits Syst. II Express Briefs 65-II(8): 1084-1088 (2018) - [c1]Mattis Hasler, Robert Wittig, Emil Matús, Gerhard P. Fettweis:
Slicing FIFOs for on-chip memory bandwidth exhaustion. ICECS 2018: 513-516
Coauthor Index
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