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2020 – today
- 2024
[j4]Ai He, Binhong Li, Jianzhong Li, Xing Zhao, Jincai Guo, Jianping Wang, Xiangqian Zeng, Yun Wang, Tianchun Ye, Quan Xue:
A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology. Microelectron. J. 151: 106337 (2024)- 2023
- [j3]Ai He
, Dashan Huang, Jiaen Li, Guofu Zhou:
Shrinking Factor Dimension: A Reduced-Rank Approach. Manag. Sci. 69(9): 5501-5522 (2023) - 2021
- [j2]Xiao Xiang, Weixin Gai, Ai He, Hang Zhou, Dong Yanchi:
Equal-slope baud-rate CDR algorithm with optimized eye opening. Microelectron. J. 114: 105138 (2021) - [j1]Ai He, Weixin Gai, Bingyi Ye, Boyang Zhang, Kai Sheng, Yuanliang Li:
56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology. Microelectron. J. 116: 105236 (2021) - [c6]Ai He, Weixin Gai, Kai Sheng, Ninghuang Li:
An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology. ASICON 2021: 1-4
2010 – 2019
- 2019
- [c5]Ai He, Weixin Gai, Yufan Feng, Zhongzhu Pu, Xiao Xiang:
Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs. ISCAS 2019: 1-4 - [c4]Xiao Xiang, Weixin Gai, Linqi Shi, Ai He, Kai Sheng:
An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation. ISCAS 2019: 1-5 - 2018
- [c3]Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang, Kai Sheng, Ai He:
A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS. ISSCC 2018: 114-116 - 2015
- [c2]Ming Jiang, Ai He, Kuangyu Wang, Zhengyi Le:
Two-Way Graphic Password for Mobile User Authentication. CSCloud 2015: 476-481 - 2013
- [c1]Ai He, Shefali Sharma, Chun-Nan Hsu:
Reconstructing Big Semantic Similarity Networks. TextGraphs@EMNLP 2013: 20-28
Coauthor Index
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