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ORCIDSoo-In Cho
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- affiliation: Samsung Electronics Company Ltd., Hwasung, South Korea
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2000 – 2009
- 2009
[j21]Byung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho:
A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces. IEEE J. Solid State Circuits 44(5): 1522-1530 (2009)- 2008
- [j20]Seung-Jun Bae, Kwang-Il Park, Jeong-Don Ihm, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Yoon-Sik Park, Min-Sang Park, Hong-Kyong Lee, Sam-Young Bang, Gil-Shin Moon, Seokwon Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim
, Ji-Hoon Lim, Jae-Sung Kim, Sunghoon Kim, Seong-Jin Jang, Joo-Sun Choi, Young-Hyun Jun, Kinam Kim, Soo-In Cho:
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. IEEE J. Solid State Circuits 43(1): 121-131 (2008) - 2007
- [c3]Jeong-Don Ihm, Seung-Jun Bae, Kwang-Il Park, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Ho-Kyung Lee, Min-Sang Park, Sam-Young Bang, Mi-Jin Lee, Gil-Shin Moon, Young-Wook Jang, Suk-Won Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim, Ji-Hoon Lim, Jae-Sung Kim, Su-Jin Park, Ok-Joo Park, Se-Mi Yang, Jin-Yong Choi, Young-Wook Kim, Hyun-Kyu Lee, Sunghoon Kim, Seong-Jin Jang, Young-Hyun Jun, Soo-In Cho:
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. ISSCC 2007: 492-617 - [c2]Byung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho:
A DLL with Jitter-Reduction Techniques for DRAM Interfaces. ISSCC 2007: 496-497 - 2006
- [j19]Churoo Park, Hoeju Chung, Yun-Sang Lee, Jaekwan Kim, JaeJun Lee, Moo Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Ki-Whan Song, Kyu-Hyoun Kim, Jung-Bae Lee, Changhyun Kim, Soo-In Cho:
A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. IEEE J. Solid State Circuits 41(4): 831-838 (2006) - 2005
- [j18]Sang-Bo Lee, Seong-Jin Jang, Jin-Seok Kwak, Sang-Jun Hwang, Young-Hyun Jun, Soo-In Cho, Chil-Gee Lee:
A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control. IEEE J. Solid State Circuits 40(1): 223-232 (2005) - [j17]Joseph T. Kennedy, Randy Mooney, Robert Ellis, James E. Jaussi, Shekhar Borkar, Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Steffen Loeffler, Jochen Hoffmann, Wolfgang Hokenmaier, Russ Houghton, Thomas Vogelsang:
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. IEEE J. Solid State Circuits 40(1): 233-244 (2005) - 2003
- [j16]Jae-Yoon Sim, Hongil Yoon, Ki-Chul Chun, Hyun-Seok Lee, Sang-Pyo Hong, Kyu-Chan Lee, Jei-Hwan Yoo, Dong-Il Seo, Soo-In Cho:
A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor. IEEE J. Solid State Circuits 38(4): 631-640 (2003) - [c1]Young-Soo Sohn, Seung-Jun Bae, Hong-June Park, Changhyun Kim, Soo-In Cho:
A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation. CICC 2003: 473-476 - 2002
- [j15]Jae-Yoon Sim, Jang-Jin Nam, Young-Soo Sohn, Hong-June Park, Chang-Hyun Kim, Soo-In Cho:
A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme. IEEE J. Solid State Circuits 37(2): 245-250 (2002) - 2001
- [j14]Kyehyun Kyung, Hi-Choon Lee, Ki-Whan Song, Ho-Sung Song, Keewook Jung, Joon-Seo Moon, Byoung-Sul Kim, Sung-Burn Cho, Changhyun Kim, Soo-In Cho:
A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity. IEEE J. Solid State Circuits 36(5): 735-743 (2001) - [j13]Yeon-Jae Jung, Seung-Wook Lee, Daeyun Shim, Wonchan Kim, Changhyun Kim, Soo-In Cho:
A dual-loop delay-locked loop using multiple voltage-controlled delay lines. IEEE J. Solid State Circuits 36(5): 784-791 (2001) - 2000
- [j12]Jae Joon Kim, Sang-Bo Lee, Tae-Sung Jung, Chang-Hyun Kim, Soo-In Cho, Beomsup Kim:
A low-jitter mixed-mode DLL for high-speed DRAM applications. IEEE J. Solid State Circuits 35(10): 1430-1436 (2000)
1990 – 1999
- 1999
- [j11]Jae-Yoon Sim, Young-Soo Sohn, Seung-Chan Heo, Hong-June Park, Soo-In Cho:
A 1-Gb/s bidirectional I/O buffer using the current-mode scheme. IEEE J. Solid State Circuits 34(4): 529-535 (1999) - [j10]Changhyun Kim, Kye-Hyun Kyung, W.-P. Jeong, J.-S. Kim, Byung-Sik Moon, Joon-Wan Chai, S.-M. Yim, Jung-Hwan Choi, K.-H. Han, C.-J. Park, Hong-Sun Hwang, H. Choi, Sung-Burn Cho, Clemenz L. Portmann, Soo-In Cho:
A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface. IEEE J. Solid State Circuits 34(5): 645-652 (1999) - [j9]Hongil Yoon, Gi-Won Cha, Changsik Yoo, Nam-Jong Kim, Keum-Yong Kim, Chang Ho Lee, Kyu-Nam Lim, Kyuchan Lee, Jun-Young Jeon, Tae Sung Jung, Hongsik Jeong, Tae-Young Chung, Kinam Kim, Soo-In Cho:
A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM. IEEE J. Solid State Circuits 34(11): 1589-1599 (1999) - 1998
- [j8]Kyu-Chan Lee, Changhyun Kim, Hongil Yoon, Keum-Yong Kim, Byung-Sik Moon, Sang-Bo Lee, Jung-Hwa Lee, Nam-Jong Kim, Soo-In Cho:
A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme. IEEE J. Solid State Circuits 33(5): 779-786 (1998) - [j7]Chang-Hyun Kim, Jung-Hwa Lee, J. B. Lee, Beomsup Kim, C. S. Park, Sang-Bo Lee, S. Y. Lee, C. W. Park, J. G. Roh, Hyoung Sik Nam, D. Y. Kim, D. Y. Lee, Tae-Sung Jung, Hongil Yoon, Soo-In Cho:
A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system. IEEE J. Solid State Circuits 33(11): 1703-1710 (1998) - 1997
- [j6]Kyu-Chan Lee, Changhyun Kim, Dong-Ryul Ryu, Jai-Hoon Sim, Sang-Bo Lee, Byung-Sik Moon, Keum-Yong Kim, Nam-Jong Kim, Seung-Moon Yoo, Hongil Yoon, Jei-Hwan Yoo, Soo-In Cho:
Low-voltage, high-speed circuit designs for gigabit DRAMs. IEEE J. Solid State Circuits 32(5): 642-648 (1997) - 1996
- [j5]Jei-Hwan Yoo, Chang-Hyun Kim, Kyu-Chan Lee, Kye-Hyun Kyung, Seung-Moon Yoo, Jung-Hwa Lee, Moon-Hae Son, Jin-Man Han, Bok-Moon Kang, Ejaz Haq, Sang-Bo Lee, Jai-Hoon Sim, Joung-Ho Kim, Byung-Sik Moon, Keum-Yong Kim, Jae-Gwan Park, Kyu-Phil Lee, Kang-Yoon Lee, Ki-Nam Kim, Soo-In Cho, Jong-Woo Park, Hyung-Kyu Lim:
A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth. IEEE J. Solid State Circuits 31(11): 1635-1644 (1996) - 1994
- [j4]Yunho Choi, Myungho Kim, Hyunsoon Jang, Taejin Kim, Seung-hoon Lee, Ho-cheol Lee, Churoo Park, Siyeol Lee, Cheol-soo Kim, Soo-In Cho, Ejaz Haq, J. Karp, Daeje Chin:
16-Mb synchronous DRAM with 125-Mbyte/s data rate. IEEE J. Solid State Circuits 29(4): 529-533 (1994) - 1993
- [j3]Seung-Moon Yoo, Ejaz Haq, Seung-Hoon Lee, Yun-Ho Choi, Soo-In Cho, Nam-Soo Kang, Daeje Chin:
Variable V/sub CC/ design techniques for battery-operated DRAMs. IEEE J. Solid State Circuits 28(4): 499-503 (1993) - 1992
- [j2]Dong-Sun Min, Soo-In Cho, Dong Soo Jun, Dong-Jae Lee, Yongsik Seok, Daeje Chin:
Temperature-compensation circuit techniques for high-density CMOS DRAMs. IEEE J. Solid State Circuits 27(4): 626-631 (1992)
1980 – 1989
- 1989
- [j1]Daeje Chin, Changhyun Kim, Yunho Choi, Dong-Sun Min, Hong-Sun Hwang, Hoon Choi, Soo-In Cho, Tae-Young Chung, Chan J. Park, Yunseung Shin, Kwang Pyuk Suh, Yong E. Park:
An experimental 16-Mbit DRAM with reduced peak-current noise. IEEE J. Solid State Circuits 24(5): 1191-1197 (1989)
Coauthor Index
aka: Changhyun Kim
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