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ORCIDIEEE Micro, Volume 31
Volume 31, Number 1, January - February 2011
- Erik R. Altman:
A Solid Past, A Vital Future. 4-5 - Yale N. Patt, Onur Mutlu:
Top Picks [Guest editors' introduction]. 6-10 - Doe Hyun Yoon, Mattan Erez
:
Virtualized ECC: Flexible Reliability in Main Memory. 11-19 - Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David M. Brooks:
Voltage Noise in Production Processors. 20-28 - Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das:
Aérgia: A Network-on-Chip Exploiting Packet Latency Slack. 29-41 - John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel:
Cohesion: An Adaptive Hybrid Memory Model for Accelerators. 42-55 - M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt:
Data Marshaling for Multicore Systems. 56-64 - Matthew A. Watkins, David H. Albonesi:
ReMAP: A Reconfigurable Architecture for Chip Multiprocessors. 65-77 - Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter:
Thread Cluster Memory Scheduling. 78-89 - Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John:
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue. 90-98 - Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar R. Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian:
CHOP: Integrating DRAM Caches for CMP Server Platforms. 99-108 - Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin:
Address Translation Aware Memory Consistency. 109-118 - Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee:
Security Refresh: Protecting Phase-Change Memory against Malicious Wear Out. 119-127 - Shane Greenstein:
Digital Dark Matter. 128
Volume 31, Number 2, March - April 2011
- Erik R. Altman:
Hot Chips and Remembering a Pioneer. 3 - Jose Renau, Will Eatherton:
Hot Chips 22. 4-5 - Michael Butler, Leslie Barnes, Debjit Das Sarma, Bob Gelinas:
Bulldozer: An Approach to Multithreaded Compute Performance. 6-15 - Brad Burgess, Brad Cohen, Marvin Denman, Jim Dundas, David Kaplan, Jeff Rupley:
Bobcat: AMD's Low-Power x86 Processor. 16-25 - Brian W. Curran, Lee Eisen, Eric M. Schwarz, Pak-kin Mak, James D. Warnock, Patrick J. Meaney, Michael F. Fee:
The zEnterprise 196 System and Microprocessor. 26-40 - Olav Lindtjorn, Robert G. Clapp, Oliver Pell, Haohuan Fu, Michael J. Flynn, Oskar Mencer:
Beyond Traditional Microprocessors for Geoscience High-Performance Computing Applications. 41-49 - Craig M. Wittenbrink, Emmett Kilgariff, Arjun Prabhu:
Fermi GF100 GPU Architecture. 50-59 - Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, José A. Tierno, Pradip Bose, Alper Buyuktosunoglu:
Introducing the Adaptive Energy Management Features of the Power7 Chip. 60-75 - Jeffrey Brown, Sandra Woodward, Brian Bass, Charlie Johnson:
IBM Power Edge of Network Processor: A Wire-Speed System on a Chip. 76-85 - Nathan Goulding-Hotta, Jack Sampson, Ganesh Venkatesh, Saturnino Garcia, Joe Auricchio, Po-Chao Huang, Manish Arora, Siddhartha Nath, Vikram Bhatt, Jonathan Babb, Steven Swanson, Michael B. Taylor:
The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future. 86-95 - Richard H. Stern:
Standardization Skullduggery Revisited. 96-99 - Richard Mateosian:
Technology. 100-102 - Shane Greenstein:
The Direction of Broadband Spillovers. 104
Volume 31, Number 3, May - June 2011
- Erik R. Altman:
Very Large-Scale Systems and Some History. 2-3 - Natalie D. Enright Jerger, Mikko H. Lipasti:
Systems for Very Large-Scale Computing. 4-7 - Ron O. Dror, J. P. Grossman, Kenneth M. Mackenzie, Brian Towles, Edmond Chow, John K. Salmon, Cliff Young, Joseph A. Bank, Brannon Batson, Martin M. Deneroff, Jeffrey Kuskin, Richard H. Larson, Mark A. Moraes, David E. Shaw:
Overcoming Communication Latency Barriers in Massively Parallel Scientific Computation. 8-19 - Ravi R. Iyer, Sadagopan Srinivasan, Omesh Tickoo, Zhen Fang, Ramesh Illikkal, Steven Zhang, Vineet Chadha, Paul M. Stillwell, Seung Eun Lee:
CogniServe: Heterogeneous Server Architecture for Large-Scale Recognition. 20-31 - Juan Gonzalez, Judit Giménez, Marc Casas, Miquel Moretó, Alex Ramírez, Jesús Labarta, Mateo Valero:
Simulating Whole Supercomputer Applications. 32-45 - Stijn Polfliet, Frederick Ryckbosch, Lieven Eeckhout:
Automated Full-System Power Characterization. 46-59 - Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Eren Kursun, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero:
Energy-Aware Accounting and Billing in Large-Scale Computing Facilities. 60-71 - Enrico Bini, Giorgio C. Buttazzo, Johan Eker, Stefan Schorr, Raphael Guerra, Gerhard Fohler, Karl-Erik Årzén, Vanessa Romero, Claudio Scordino:
Resource Management on Multicore Systems: The ACTORS Approach. 72-81 - Wei Huang, Malcolm Allen-Ware, John B. Carter, Mircea R. Stan, Edmund Cheng:
Temperature-Aware Architecture: Lessons and Opportunities. 82-86 - Shane Greenstein:
The Open Internet Order. 88
Volume 31, Number 4, July - August 2011
- Erik R. Altman:
Big Chips and Beyond. 2 - Andrew B. Kahng, Vijayalakshmi Srinivasan:
Big Chips. 3-5 - Nikos Hardavellas, Michael Ferdman, Babak Falsafi, Anastasia Ailamaki:
Toward Dark Silicon in Servers. 6-15 - Wei Huang, Karthick Rajamani, Mircea R. Stan, Kevin Skadron:
Scaling with Design Constraints: Predicting the Future of Big Chips. 16-29 - Daniel R. Johnson, Matthew R. Johnson, John H. Kelm, William Tuohy, Steven S. Lumetta, Sanjay J. Patel:
Rigel: A 1, 024-Core Single-Chip Accelerator Architecture. 30-41 - Junli Gu, Yihe Sun, Steven S. Lumetta, Rakesh Kumar:
MOPED: Accelerating Data Communication on Future CMPs. 42-50 - David A. Papa, Charles J. Alpert, Cliff C. N. Sze, Zhuo Li, Natarajan Viswanathan, Gi-Joon Nam, Igor L. Markov:
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. 51-62 - Ayse K. Coskun, David Atienza, Mohamed M. Sabry, Jie Meng:
Attaining Single-Chip, High-Performance Computing through 3D Systems with Active Cooling. 63-75 - Richard W. Vuduc, Kent Czechowski:
What GPU Computing Means for High-End Systems. 74-78 - Shane Greenstein:
An Honest Policy Wonk. 80
Volume 31, Number 5, 2011
- Erik R. Altman:
CPUs and GPUs: Who Owns the Future? 2-3 - David M. Brooks:
CPUs, GPUs, and Hybrid Computing. 4-6 - Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco:
GPUs and the Future of Parallel Computing. 7-17 - David Rohr, Matthias Bach, Matthias Kretz, Volker Lindenstruth:
Multi-GPU DGEMM and High Performance Linpack on Highly Energy-Efficient Clusters. 18-27 - Siegfried Benkner, Sabri Pllana, Jesper Larsson Träff, Philippas Tsigas, Uwe Dolinsky, Cédric Augonnet, Beverly Bachmayer, Christoph W. Kessler, David Moloney, Vitaly Osipov:
PEPPHER: Efficient and Productive Usage of Hybrid Computing Systems. 28-41 - HyoukJoong Lee, Kevin J. Brown, Arvind K. Sujeeth, Hassan Chafi, Tiark Rompf, Martin Odersky, Kunle Olukotun:
Implementing Domain-Specific Languages for Heterogeneous Parallel Computing. 42-53 - Hayden Kwok-Hay So, Junying Chen, Billy Y. S. Yiu, Alfred C. H. Yu:
Medical Ultrasound Imaging: To GPU or Not to GPU? 54-65 - Jeremy S. Meredith, Philip C. Roth, Kyle Spafford, Jeffrey S. Vetter:
Performance Implications of Nonuniform Device Topologies in Scalable Heterogeneous Architectures. 66-75 - Richard Mateosian:
Effective Communication [review of ".....Trees, Maps, and Theorems: Effective Commuincation for Rational Minds" (Doumont, J.-L.; 2009)]. 76-78 - Shane Greenstein:
The Wi-Fi Journey. 80
Volume 31, Number 6, November - December 2011
- Erik R. Altman:
New Blood, Cool Chips, and Heterogeneous Designs. 2-3 - Makoto Ikeda, Fumio Arakawa:
Cool Chips. 4-5 - Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo:
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. 6-18 - Tomoya Suzuki, Hideki Yamada, Toshiyuki Yamagishi, Daisuke Takeda, Koji Horisaki, Tom Vander Aa, Toshio Fujisawa, Liesbet Van der Perre, Yasuo Unekawa:
High-Throughput, Low-Power Software-Defined Radio Using Reconfigurable Processors. 19-28 - Craig Court, Paul Kelly:
Loop-Directed Mothballing: Power Gating Execution Units Using Runtime Loop Analysis. 29-38 - Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Toshihiro Hanawa, Shin'ichi Miura, Taisuke Boku:
Peach: A Multicore Communication System on Chip with PCI Express. 39-50 - Hiroshi Shimamoto, Takayuki Yamashita, Misao Kubota, Hirotaka Maruyama:
Advanced Camera Technologies for Broadcasting. 51-57 - Greg Stitt:
Are Field-Programmable Gate Arrays Ready for the Mainstream? 58-63 - Shane Greenstein:
Steve Jobs and the Economics of One Entrepreneur. 64-65
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