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ORCID19th PATMOS 2009: Delft, The Netherlands
- José Monteiro, Rene van Leuken:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 19th International Workshop, PATMOS 2009, Delft, The Netherlands, September 9-11, 2009, Revised Selected Papers. Lecture Notes in Computer Science 5953, Springer 2010, ISBN 978-3-642-11801-2
Keynotes
- Toby Doorn, Roelof Salters:
Robust Low Power Embedded SRAM Design: From System to Memory Cell. 1 - Davide Pandini:
Variability in Advanced Nanometer Technologies: Challenges and Solutions. 2 - Yusuf Leblebici:
Subthreshold Circuit Design for Ultra-Low-Power Applications. 3
Special Session
- Martin Barnasconi, Markus Damm, Karsten Einwich:
SystemC AMS Extensions: New Language - New Methods - New Applications. 4
Variability & Statistical Timing
- Mohsen Raji
, Behnam Ghavami, Hamid R. Zarandi, Hossein Pedram:
Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation. 5-15 - Zeqin Wu, Philippe Maurine, Nadine Azémard, Gilles R. Ducharme:
Interpreting SSTA Results with Correlation. 16-25 - Ioannis Kouretas, Vassilis Paliouras:
Residue Arithmetic for Variation-Tolerant Design of Multiply-Add Units. 26-35 - Paul Zuber, Vladimir Matvejev, Philippe Roussel, Petr Dobrovolný, Miguel Miranda:
Exponent Monte Carlo for Quick Statistical Circuit Simulation. 36-45
Poster Session: Circuit Level Techniques
- Monica Figueiredo, Rui L. Aguiar:
Clock Repeater Characterization for Jitter-Aware Clock Tree Synthesis. 46-55 - Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu, Shuhei Higashi:
A Hardware Implementation of the User-Centric Display Energy Management. 56-65 - Wei Liu, Andrea Calimera, Alberto Nannarelli, Enrico Macii, Massimo Poncino:
On-chip Thermal Modeling Based on SPICE Simulation. 66-75 - Javier Castro-Ramirez, Pilar Parra Fernández, Antonio J. Acosta:
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. 76-85
Power Management
- Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris:
Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip. 86-95 - Alberto Bonanno, Alberto Bocca, Alberto Macii, Enrico Macii, Massimo Poncino:
Data-Driven Clock Gating for Digital Filters. 96-105 - Howard Chen, Indira Nair:
Power Management and Its Impact on Power Supply Noise. 106-115 - Muhammad Khurram Bhatti, Muhammad Farooq, Cécile Belleudy, Michel Auguin, Ons Mbarek:
Assertive Dynamic Power Management (AsDPM) Strategy for Globally Scheduled RT Multiprocessor Systems. 116-126
Low Power Circuits & Technology
- Chih-Hsiang Lin, James B. Kuo:
Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique. 127-135 - Ritej Bachhawat, Pankaj Golani, Peter A. Beerel:
Crosstalk in High-Performance Asynchronous Designs. 136-145 - Tomasz Król, Milos Krstic, Xin Fan, Eckhard Grass:
Modeling and Reducing EMI in GALS and Synchronous Systems. 146-155 - Hossein Karimiyan, Sayed Masoud Sayedi, Hossein Saidi:
Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop. 156-164
Poster Session: System Level Techniques
- Nikolaos Zompakis, Martin Trautmann, Alexandros Bartzas, Stylianos Mamagkakis, Dimitrios Soudris, Liesbet Van der Perre, Francky Catthoor:
Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms. 165-174 - Alexandros Bartzas, Christos Baloukas, Dimitrios Soudris, Konstantinos Potamianos, Fragkiskos Ieromnimon, Nikolaos S. Voros:
Dynamic Data Type Optimization and Memory Assignment Methodologies. 175-185 - Christian Bachmann, Andreas Genser, Christian Steger, Reinhold Weiß, Josef Haid:
Accelerating Embedded Software Power Profiling Using Run-Time Power Emulation. 186-195 - Newsha Ardalani, Amirali Baniasadi:
Write Invalidation Analysis in Chip Multiprocessors. 196-205 - Marius Gligor, Nicolas Fournel, Frédéric Pétrot, Fabien Colas-Bigey, Anne-Marie Fouilliart, Philippe Teninge, Marcello Coppola:
Practical Design Space Exploration of an H264 Decoder for Handheld Devices Using a Virtual Platform. 206-215 - Tom English, Ka Lok Man, Emanuel M. Popovici:
BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation. 216-226
Power & Timing Optimization Techniques
- Gaurang Upasani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. 227-236 - Thomas Schweizer, Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel:
Low Energy Voltage Dithering in Dual VDD Circuits. 237-246 - Nabila Moubdi, Philippe Maurine, Robin Wilson, Nadine Azémard, Vincent Dumettier, Abhishek Bansal, Sebastien Barasinski, Alain Tournier, Guy Durieu, David Meyer, Pierre Busson, Sarah Verhaeren, Sylvain Engels:
Product On-Chip Process Compensation for Low Power and Yield Enhancement. 247-255
Self-timed Circuits
- Hossein Karimiyan Alidash, Vojin G. Oklobdzija:
Low-Power Soft Error Hardened Latch. 256-265 - Bettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard:
Digital Timing Slack Monitors and Their Specific Insertion Flow for Adaptive Compensation of Variabilities. 266-275 - Yuri Stepchenkov, Yuri Diachenko, Victor N. Zakharov, Yuri Rogdestvenski, Nikolai Morozov, Dmitri Stepchenkov:
Quasi-Delay-Insensitive Computing Device: Methodological Aspects and Practical Implementation. 276-285 - Delong Shang, Fei Xia, Stanislavs Golubcovs, Alexandre Yakovlev:
The Magic Rule of Tiles: Virtual Delay Insensitivity. 286-296
Low Power Circuit Analysis & Optimization
- Sidinei Ghissoni, João Baptista dos Santos Martins, Ricardo Augusto da Luz Reis, José C. Monteiro:
Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates. 297-306 - Milena Vratonjic, Matthew M. Ziegler, George Gristede, Victor V. Zyuban, Thomas Mitchell, Ee Cho, Chandu Visweswariah, Vojin G. Oklobdzija:
A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). 307-316 - Paulo F. Butzen, André Inácio Reis, Renato P. Ribas:
Routing Resistance Influence in Loading Effect on Leakage Analysis. 317-325
Low Power Design Studies
- Néstor Suárez, Gustavo M. Callicó, Roberto Sarmiento, Octavio Santana, Anteneh A. Abbo:
Processor Customization for Software Implementation of the AES Algorithm for Wireless Sensor Networks. 326-335 - Motoi Ichihashi, Hélène Lhermet, Edith Beigné, Frédéric Rothan, Marc Belleville, Amara Amara:
An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. 336-346 - Joachim Neves Rodrigues, Omer Can Akgun, Puneet Acharya, Adolfo de la Calle, Yusuf Leblebici, Viktor Öwall:
Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding. 347-356 - Fabio Frustaci, Marco Lanuzza:
A New Optimized High-Speed Low-Power Data-Driven Dynamic (D3L) 32-Bit Kogge-Stone Adder. 357-366
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