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ORCIDISOCC 2017: Seoul, South Korea
- International SoC Design Conference, ISOCC 2017, Seoul, South Korea, November 5-8, 2017. IEEE 2017, ISBN 978-1-5386-2285-8
- Byungki Han, Jongwoo Lee, Seunghyun Oh, Jae-Kwon Kim, Eswar Mamidala, Thomas Byunghak Cho:
A 14nm FinFET analog baseband SOC for multi-mode cellular applications with tri-band carrier aggregation. 1-2 - Nahid Mirzaie, Ahmed Alzahmi, Chung-Ching Lin, Insoo Kim, Gyung-Su Byun:
A low-power and performance-efficient SAR ADC design. 3-4 - Yung-Hui Chung, Ya-Mien Hsu, Chia-Wei Yen, Wei-Shu Rih:
A 12-bit 160-MS/s ping-pong subranged-SAR ADC in 65nm CMOS. 5-6 - Hao-Min Lin, Kuei-Ann Wen:
A low power reconfigurable SAR ADC for CMOS MEMS sensor. 7-8 - Daxiang Li, Yang Zhang, Debajit Basak, Kong-Pang Pun:
Continuous-time delta-sigma modulator with an upfront passive-RC low-pass network. 9-10 - Donghyun Han
, Hayoung Lee, Donghyun Kim, Sungho Kang:
A new repair scheme for TSV-based 3D memory using base die repair cells. 11-12 - Madhusudan Singh, Shiho Kim:
Security analysis of intelligent vehicles: Challenges and scope. 13-14 - Madhusudan Singh, Shiho Kim:
Introduce reward-based intelligent vehicles communication using blockchain. 15-16 - Hidekuni Takao:
High resolution tactile sensing with silicon MEMS sensors for measurement of fingertip sensation. 17-18 - Tsung-Yi Tsai, Hsiang-Yu Shih, Chua-Chin Wang:
A pipeline ROM-less DDFS using equal-division interpolation. 19-20 - Prashanthi Metku, Ramu Seva, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Low-power null convention logic design based on modified gate diffusion input technique. 21-22 - Y. Sudha Vani, N. Usha Rani, Ramesh Vaddi:
A low voltage capacitor based current controlled sense amplifier for input offset compensation. 23-24 - Hong-Fu Chou, Chiu-Wing Sham:
Unequal protection approach for RLL-constrained LDPC coded recording system using deliberate flipping. 25-26 - Hyunyul Lim, Tae Hyun Kim, Dongsu Lee, Sungho Kang:
LARECD: Low area overhead and reliable error correction DMR architecture. 27-28 - Merritt Miller, Aditya Dalakoti, Prashansa Mukim, Forrest Brewer:
Low phase noise pulse rotary wave voltage controlled oscillator. 29-30 - Tsung-Ying Wu, Jeng-Rern Yang:
A multiband fully integrated high-linearity power amplifier using a 0.18-μm CMOS process for LTE applications. 31-32 - Shinil Chang, Yongho Lee, Hyunchol Shin:
Design of a 2.4-GHz 2.2-mW CMOS RF receiver front-end for BLE applications. 33-34 - Gyu-Sup Won, Dong-Soo Lee, SungHun Cho, Kang-Yoon Lee:
Design of power-efficient class-D CMOS power amplifier with resistor feedback. 35-36 - Jui-Cheng Hsiao, Dai-En Jhou, Tai-Cheng Lee:
A 10-Gb/s equalizer with digital adaptation. 38-39 - Yalong Pang, Jun Han, Jianmin Zeng, Yujie Huang, Xiaoyang Zeng:
Instruction set extension and hardware acceleration for SVM application toward a vector processor. 42-43 - Yongshin Kang, Jaeyong Chung:
A dynamic fixed-point representation for neuromorphic computing systems. 44-45 - Subin Huh, Joonsang Yu, Kiyoung Choi:
A new stochastic mutiplier for deep neural networks. 46-47 - Soeb Hussain, Rupal Saxena, Xie Han, Jameel Ahmed Khan, Hyunchul Shin:
Hand gesture recognition using deep learning. 48-49 - Mohamed Khairy Bahry, Mohamed El-Nozahi, Emad Hegazi:
A battery-connected all-digital capacitive DC-DC converter with load tracking controller. 51-52 - Yaya Chen, Yan Han, Shifeng Zhang, Tianlin Cao, Xiaoxia Han, Ray C. C. Cheung:
High DC gain and wide output swing class-C inverter. 53-54 - A. N. Ragheb, HyungWon Kim:
Nano-second scale dynamic voltage scaler based on charge-pump and BW-DAC. 55-56 - Bum-Sik Chung, Hyeong-Kyu Kim, Kang-Il Cho, Ho-Jin Kim, Gil-Cho Ahn:
Analog front-end for EMG acquisition system. 57-58 - Shusuke Yanagawa, Ryota Shimizu, Mototsugu Hamada, Toru Shimizu, Tadahiro Kuroda:
Wireless power transfer to stacked modules for IoT sensor nodes. 59-60 - Menghan Sun, Derek Abbott, Said F. Al-Sarawi:
A fully integrable RF energy harvester with dynamic efficiency tuning. 61-62 - Kazutami Arimoto, Daichi Yamashita, Nao Igawa, Tomoyuki Yokogawa, Yoichiro Sato, Isao Kayano, Akio Shiratori:
A smart low power R-R-I heartbeat monitor system with contactless UWB sensor. 63-64 - Kyungmin Lee, Ipoom Jeong, Won Woo Ro:
Parallel in-order execution architecture for low-power processor. 65-66 - Ryota Shimizu, Shusuke Yanagawa, Toru Shimizu, Mototsugu Hamada, Tadahiro Kuroda:
Convolutional neural network for industrial egg classification. 67-68 - Sung-Wook Eo, Joon Goo Lee, Min-Seok Kim, Young-Chai Ko:
High performance and low power timing controller design for LCoS microdisplay system. 71-72 - Ramu Seva, Prashanthi Metku, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
Variable bit truncation technique for approximate stochastic computing (ASC). 73-74 - Ki-Deok Kim, ByeongGi Jang, Sung Jin Oh, Kang-Yoon Lee:
Design of high efficiency of 98 percent active rectifier with automatic zero voltage and current switching circuit for wireless charging system. 75-76 - Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Makoto Nakamura:
Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS. 77-78 - Astrie Nurasyeila Fifie Asli, Yan Chiew Wong:
-23.5dBm senstivity, 900MHz differential-drive rectifier. 79-80 - Minsu Jeong, Ockgoo Lee, Soo-Won Kim:
WLAN transceiver for 802.11 a/b/g/n/ac with integrated power amplifier and harmonic LO frequency VCO. 81-82 - Kwanghee Chang, Minsik Kim, Kyungah Kim, Won Woo Ro:
Characterizing convolutional neural network workloads on a detailed GPU simulator. 84-85 - Dinh Van Luan, Nguyen Xuan Truong, Hyun Kim, Hyuk-Jae Lee:
Implementation of the XY2-100 protocol on low-cost microcontroller. 86-87 - Yuya Hirai, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa:
A selector-based FFT processor and its FPGA implementation. 88-89 - Huey Woan Lim, Yuan Wen Hau, Mohd Afzan Othman, Chiao Wen Lim:
Embedded system-on-chip design of atrial fibrillation classifier. 90-91 - Trio Adiono, Angga Pratama Putra:
Hardware/software model of DCO-OFDM based visible light communication SoC using DMA. 92-93 - Keunyeol Park, Minhyun Jin, Soo Youn Kim, Minkyu Song:
Design of a high speed CMOS image sensor with a hybrid single-slope column ADC and a finite state machine. 95-96 - Yu Zou, Massimo Gottardi, Michela Lecca:
A 1.6mW 320×240 pixel vision sensor for event detection. 97-98 - Bing Li, Lin-Fa Ma, Wei Wang, Ji-Ping Na, Chuang Li:
A high-sensitivity signal conditioning interface for capacitive touch key using ΔΣ modulation. 99-100 - Yuki Yahagi, Masao Yanagisawa, Nozomu Togawa:
Robust AES circuit design for delay variation using suspicious timing error prediction. 101-102 - Wonseok Choi, Jongsun Park:
An efficient convolutional neural networks design with heterogeneous SRAM cell sizing. 103-104 - Keewon Cho, Young-Woo Lee, Sungyoul Seo, Sungho Kang:
An efficient built-in self-repair scheme for area reduction. 105-106 - Kyungseon Cho, Seungjin Lee, Choong Keun Lee, Taegun Yim, Hongil Yoon:
Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA. 107-108 - Ahmed Alzahmi, Nahid Mirzaie, Chung-Ching Lin, Insoo Kim, Gyung-Su Byun:
High-performance RF-interconnect for 3D stacked memory. 109-110 - Abhishek Shrivastava, Amandeep Kaur, Mukul Sarkar:
A 1.2 V, 33 ppm/°C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs. 111-112 - Koichi Saito, Akio Shimizu, Yohei Ishikawa, Takuro Noguchi, Sumio Fukai:
Multiple output variable overdrive voltage CMOS current mirror. 113-114 - Liangduo Peng, Yuan Cao, Xiaofang Pan, Xiaojin Zhao:
A low-power relaxation oscillator with improved thermal stability. 115-116 - Ruhaifi Abdullah Zawawi, Nuha A. Rhaffor, Shukri Korakkottil Kunhi Mohd, Sofiyah Sal Hamid, Asrulnizam Bin Abd Manaf, Kazuaki Sawada:
A CMOS bandgap voltage reference with current-control circuits for the extended operating temperature range. 117-118 - Mohamed B. Elamien, Soliman A. Mahmoud:
A 1 MHz-10.2 MHz BW/0 dB-70 dB gain DPOTA-based baseband chain receiver. 119-120 - Hyunggoy Oh, Heetae Kim, Jaeil Lim, Sungho Kang:
A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. 121-122 - Hyeonchan Lim, Junghwan Kim, Soyeon Kang, Sungho Kang:
Test data reduction method based on berlekamp-massey algorithm. 123-124 - Jindun Dai, Wenda Ma, Xin Jiang, Takahiro Watanabe:
Hybrid path-diversity-dominant output selection method for Network-on-Chip systems. 125-126 - Ronnie O. Serfa Juan, Byoung Hwan Ko, Chan Su Park, Hi-Seok Kim:
Development of a reduction algorithm for CAN frame bits. 127-128 - Meng Liu, Zhiwei Zhang, Wenqin Sun, Donglin Wang:
Optimization of clock mesh based on wire sizing variation. 129-130 - Tso-Bing Juang, Ying-Ren Lee:
Low-area implementations of concurrent error detection logarithmic processors. 131-132 - Qilei Ren, Ka Lok Man, Eng Gee Lim, Jinkyung Lee, Kyung Ki Kim:
Cooperation of multi robots for disaster rescue. 133-134 - Cheng Zhu, Zhao Wang, Mark Leach, Ka Lok Man, Eng Gee Lim:
Mobile phone antenna. 135-136 - Minming Gu, ZhenPing Xia, Yan Lei, Lin Zhang, Jieming Ma:
Wireless low power toxic gas detector based on ADuCM360. 137-138 - Vijayakumar Nanjappan, Hai-Ning Liang, Kim Lau, Jaemin Choi, Kyung Ki Kim:
Clothing-based wearable sensors for unobtrusive interactions with mobile devices. 139-140 - Yoko Uwate, Yoshifumi Nishio:
Chaotic circuits network with scale-free coupling distribution. 142-143 - Jerald Yoo:
On-chip epilepsy detection: Where machine learning meets patient-specific healthcare. 146-147 - Yusuke Yoshida, Kimiyoshi Usami, Hideharu Amano:
Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. 148-149 - Junichiro Kadomoto, Hideharu Amano, Tadahiro Kuroda:
An inductive-coupling link for 3-D Network-on-Chips. 150-151 - Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki:
Building block multi-chip systems using inductive coupling through chip interface. 152-154 - Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano:
Scalable deep neural network accelerator cores with cubic integration using through chip interface. 155-156 - Shinsuke Hamada, Atsushi Koshiba, Mitaro Namiki, Hideharu Amano:
Building block operating system for 3D stacked computer systems with inductive coupling interconnect. 157-158 - Sanghyun Heo, Joohyeb Song, Kyoungmin Park, Eun-Ho Choi, Seong-Mun Kim, Franklin Bien:
A low-offset, low-noise, fully differential receiver with a differential signaling method for fingerprint mutual capacitive touch screen. 166-167 - Seunghun Oh, Hanho Lee:
Parallel architecture for concatenated polar-CRC codes. 173-174 - ByeongGi Jang, SeongJin Oh, Young-Jun Park, Kang-Yoon Lee:
Internal circuit offset auto compensation current sensor for wireless power systems. 176-177 - Dong-Kyu Kim, Hyun-Sik Kim:
Low-noise high-speed CMOS CID readout IC. 178-179 - Sangsu Lee, Jaehun Jun, Chulwoo Kim:
A near-threshold all-digital PLL with a bootstrapped DCO using low-dropout regulator for mitigating PVT-variations. 180-181 - Chih-Chen Peng, Jau-Ji Jou, Tien-Tsorng Shih, Chien-Liang Chiu:
High linearity transimpedance amplifier in 0.18-μm CMOS technology for 20-Gb/s PAM-4 receivers. 182-183 - JiHoon Kim, Yong Moon:
A study of low jitter phase locked loop for SPDIF. 184-185 - Sang-Hyuk Park, Kwan-Tae Kim, Kang-Yoon Lee:
Buck DC-DC converter with PFM/PWM dual mode self-tracking zero current detector. 186-187 - Kwan-Tae Kim, Sung-Jin Kim, Dong-Soo Lee, Kang-Yoon Lee:
A design of 10MHz/20MHz bandwidth baseband circuit with high performance of ACRR. 188-189 - Trio Adiono, Prasetiyo, Suksmandhira Harimurti, Khilda Afifah, Amy Hamidah Salman:
Design of highly stable bandgap reference circuit for RF power harvester module of a 13.56 MHz smart card tag IC. 190-191 - Donggyu Kim, Chan Ho Kim, Dong-Soo Lee, Kang-Yoon Lee:
Design of filter tuning circuit to compensate band width change of band pass filter by process and temperature. 192-193 - Hyunsun Mo, Daejeong Kim:
Multiple-output LDO regulator applying with constant feedback factor. 194-195 - Tzung-Je Lee, Guan-Jhang Li:
HV voltage sensor for 16 series li-ion battery cells using chopper stabilized amplifier. 196-197 - Hamed Abbasizadeh, Behnam Samadpoor Rikan, Thi Kim Nga Truong, Kwan-Tae Kim, Sung-Jin Kim, Dong-Soo Lee, Kang-Yoon Lee:
A design of ultra-low noise LDO using noise reduction network techniques. 198-199 - Behnam Samadpoor Rikan, Hamed Abbasizadeh, Thi Kim Nga Truong, Sung Jin Kim, Kang-Yoon Lee:
A low leakage retention LDO and leakage-based BGR with 120nA quiescent current. 200-201 - Danial Khan, Hamed Abbasizadeh, Zaffar Hayat Nawaz Khan, Young-Jun Park, Kang-Yoon Lee:
Design of a capacitor-less LDO with high PSRR for RF energy harvesting applications. 202-203 - Truong Thi Kim Nga, Hamed Abbasizadeh, Truong Van Cong Thuong, Kang-Yoon Lee:
A high efficiency Digital PWMDC-DC converter using hybrid control technique for EH applications. 204-205 - Syed Adil Ali Shah, Young Jun Park, Hamed Abbasizadeh, Zaffar Hayat Nawaz Khan, Danial Khan, Kang-Yoon Lee:
A high-efficiency active rectifier by using zero current sensing and deglitch circuit for inductive coupling receiver. 206-207 - Zaffar Hayat Nawaz Khan, Danial Khan, Nabeel Ahmad, Hamed Abbasizadeh, Syed Adil Ali Shah, Young Jun Park, Kang-Yoon Lee:
6-Parallel RF energy harvesting rectifier with high power conversion efficiency (PCE) for 5.8GHz 3W wireless power transfer. 208-209 - Ji Hyeon Cheon, Sung Jin Kim, Dong-Soo Lee, Kang-Yoon Lee:
Low-dropout regulator with low output peak voltage with soft-start added to bandgap reference output. 210-211 - Vijender Kumar Sharma, Hitesh Shrimali, Jai Narayan Tripathi, Rakesh Malik:
Distortion analysis for a DC-DC buck converter. 212-213 - Truong Van Cong Thuong, Young-Jun Park, Truong Thi Kim Nga, Kang-Yoon Lee:
A sub-threshold ultra-low power low-dropout regulator. 214-215 - Yung-Hui Chung, Wei-Shu Rih:
A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS. 216-217 - Muhammad Riaz ur Rehman, Behnam Samadpoor Rikan, Deeksha Verma, Imran Ali, Kang-Yoon Lee:
Modeling of second order continuous-time sigma delta modulator in LabVIEW. 218-219 - Mehdi Nasrollahpour, Chi-Hsien Yen, Sotoudeh Hamedi-Hagh:
A high-speed, low-offset and low-power differential comparator for analog to digital converters. 220-221 - Deeksha Verma, Hye-Yeong Kang, Khuram Shehzad, Muhammad Riaz ur Rehman, Kang-Yoon Lee:
Design of asynchronous SAR ADC for low power mixed signal applications. 222-223 - Khuram Shehzad, Hye-Young Kang, Deeksha Verma, Young Jun Park, Kang-Yoon Lee:
Low-power 10-bit SAR ADC using class-AB type amplifier for IoT applications. 224-225 - Yong-Chang Choi, Sang-Sun Yoo, Hyung-Joun Yoo:
A fully-digital phase modulator with phase calibration loop for high data-rate systems. 226-227 - Mihye Moon, Shinil Chang, Yongho Lee, Hyunchol Shin:
Design of a 400-MHz 1-V 1.4-mW CMOS RF receiver for MICS applications. 228-229 - Yongho Lee, Seungsoo Kim, Hyunchol Shin:
Design of a 1-V 3-mW 2.4-GHz fractional-N PLL synthesizer in 65nm CMOS. 230-231 - Dong-Shik Kim, Won-Sang Yoon, Sang-Hoon Chai:
Implementation of RF narrow band frequency synthesizer for LoRaWAN system. 232-233 - Hui Dong Lee, Cheol Ho Kim, Sunwoo Kong, Seunghyun Jang, Kwang Seon Kim, Myung-Don Kim, Bonghyuk Park:
A linear InGaP/GaAs HBT power amplifier for LTE B7 applications. 234-235 - Chan Ho Kim, Dong Gyu Kim, Dong-Soo Lee, Kang-Yoon Lee:
Design of 36 dB IRR baseband analog for Bluetooth low energy 5.0 application in 55 nm CMOS. 236-237 - Taejong Kim, Sinyoung Kim, Kuduck Kwon:
A 0.5-V 320 μW CMOS MedRadio receiver RF front-end with a current-reuse gw-boosting common gate low noise amplifier. 238-239 - Sinyoung Kim, Taejong Kim, Kuduck Kwon:
An ultra-low-power 2.4 GHz receiver RF front-end employing a RF quadrature Gm-stage for Bluetooth low energy applications. 240-241 - Sinyoung Kim, Taejong Kim, Kuduck Kwon:
A low power 2.4 GHz quadrature local oscillator buffer for Bluetooth low energy applications. 242-243 - Gyunam Jeon, Yong-Bin Kim:
A quarter-rate 3-tap DFE for 4Gbps data rate with switched-capapctiors based 1st speculative tap. 244-245 - Jin-Wook Han, Pil-Ho Lee, Yeong-Woong Kim, Sang-Dong Kim, Jin-Woo Park, Young-Chan Jang:
A clock recovery for 2.56 GSymbol/s MIPI C-PHY receiver. 246-247 - Chia-Chi Liu, Ching-Yuan Yang:
A 1.5-Gb/s adaptive equalizer with periodically embedded clock encoding for intra-panel interfaces. 248-249 - Yen-Chen Lin, Ching-Yuan Yang, James Chang:
A 1.5-Gb/s equalizer with adaptive swing controller for TFT-LCD driver. 250-251 - Dongjun Park, Junsub Yoon, Jongsun Kim:
A low-power SerDes for high-speed on-chip networks. 252-253 - Sadeque Reza Khan, Arifa Ferdousi, GoangSeog Choi:
Hardware feasible offset and gain error correction for time-interleaved ADC. 254-255 - Sumedh Dhabu, Chip-Hong Chang:
A novel scheme for information hiding at physical layer of wireless communications. 256-257 - Koki Arauchi, Shohei Maki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
Compact implementation IIR filter in FPGA for noise reduction of sensor signal. 258-259 - Seo Lin Jeong, Myung Hoon Sunwoo:
Low power BCH decoder using early termination scheme for WBAN standard. 260-261 - Imran Ali, SungHun Cho, Dong Gyu Kim, Muhammad Riaz ur Rehman, Kang-Yoon Lee:
A design of ultra low power I2C synchronous slave controller with interface voltage level independency in 180 nm CMOS technology. 262-263 - Yeon-Jin Kim, Yang Zou, Jin-Gyun Chung:
Improved CAN compression algorithm by data reordering. 264-265 - Sanghyuk Kim, Gwon Hwan An, Suk-Ju Kang:
Facial expression recognition system using machine learning. 266-267 - Yunho Park, Youngmin Kim, Youngjoo Lee:
High-performance two-step lagrange interpolation technique for 4K UHD applications. 268-269 - Sangho Yoon, Hanjoo Cho, Sang Won Cho, Young Hwan Kim:
HMD-based virtual multi-screen control system and its gesture interface. 270-271 - Sang Won Cho, Sangho Yoon, Young Hwan Kim:
Motion vector-based film mode detection for frame rate up-conversion. 272-273 - Tae-Hun Nam, Erdenetuya, Thathupara Subramanyan Kavya, Young-Min Jang, Sang-Bock Cho:
An acquisition method of distance information in direction signs. 274-275 - Chi-Hsien Wu, Jau-Ji Jou, Hsin-Wen Ting, Shao-I Chu, Bing-Hong Liu:
Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology. 276-277 - Sunghyun Kim, Youngmin Kim:
High-performance and energy-efficient approximate multiplier for error-tolerant applications. 278-279 - Wei Wang, Yuan-Yuan Xu, Chua-Chin Wang:
Dynamic power estimation for ROM-less DDFS designs using switching activity analysis. 280-281 - Yun Seok Hong, Yong-Bin Kim, Kyung Ki Kim:
Time-domain temperature sensor based on interlaced hysteresis delay cells. 282-283 - Mangi Han, Youngmin Kim:
Unpredictable 16 bits LFSR-based true random number generator. 284-285 - Minchang Kim, Jihwan Park, Joo-Hyung Chae, Hyeongjun Ko, Mino Kim, Suhwan Kim:
An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface. 286-287 - Seungjin Lee, Taegun Yim, Choong Keun Lee, Kyungseon Cho, Hongil Yoon:
Energy-efficient write circuit in STT-MRAM based look-up table (LUT) using comparison write scheme. 288-289 - T. Nagateja, Ramesh Vaddi:
Energy efficient and high throughput transceiver design in the capacitive coupling mode exploring tunnel transistors for 3D ICs. 290-291 - Seongmo Park, Byoung Gun Choi, Kwang-Il Oh, S. E. Kim, J. H. Lee, J. J. Lee, Sung Weon Kang:
Image compression based on MR-CNN (Modified Region Convolutional Neural Network). 292-293 - Seongmin Hong, Yongjun Park:
A FPGA-based neural accelerator for small IoT devices. 294-295 - Seong-Hyeon Han, Kwang-Yeob Lee:
Implemetation of image classification CNN using multi thread GPU. 296-297 - Yukui Luo, Shuai Li, Kuangyuan Sun, Raul Renteria, Ken Choi:
Implementation of deep learning neural network for real-time object recognition in OpenCL framework. 298-299 - Kuangyuan Sun, Shuai Li, Yukui Luo, Raul Renteria, Ken Choi:
Highly-efficient parallel convolution acceleration by using multiple GPUs. 300-301 - Byeong-Jun Bang, Hyun-jeong Kwon, Young Hwan Kim:
Effective sampling method for statistical leakage analysis: Hybrid sampling method. 302-303 - Young-kuen Kim, Yong Ho Song:
Impact of processor cache memory on storage performance. 304-305 - Yonatan Shoshan, Slava Yuzhaninov, Noa Edri, Shay Harari, Yehuda Rudin, Yoav Weizman, Itai Nadler, Nir Rosenberg, Benjamin Flom, Dotan Bechor, Gilad Morag, Evgeny Grigoriants, Naftaly Blum, Ronen Daly, Maya Reuveni, Alexander Fish:
A SoC platform for emerging technologies. 306-307 - Pervaiz Kareem, Asim Khan, Chong-Min Kyung:
Memory efficient self guided image filtering. 308-309 - Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine:
FPGA-based transceiver circuit for labeling signal transmission system. 310-311 - Jung-Hwan Oh, Jong Uk Wi, Seung Eun Lee:
Design of CAN - CAN FD bridge for in-vehicle network. 312-313 - Mohamed B. Elamien, Soliman A. Mahmoud:
A highly linear DPOTA-based configurable analog front-end for EXG (EEG, ECG, and EMG). 314-315 - Vo Nhut Tuan, Hyouk-Kyu Cha:
A standard CMOS neural stimulator IC with high voltage compliant output current driver. 316-317 - Fatia Uftiani Putri, Hyouk-Kyu Cha:
A low-power low-noise ultrasonic receiver front-end IC for medical imaging systems. 318-319 - Hyoung-Ro Lee, Chi-Ho Lin, Ki-Hyuk Park, Won-Jong Kim, Han-Jin Cho:
Development of SoC virtual platform for IoT terminals based on OneM2M. 320-321 - Aditya Dalakoti, Merritt Miller, Forrest Brewer:
High performance pulse ring voltage controlled oscillator for Internet of Things. 322-323
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