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ORCIDHLDVT 2012: Huntington Beach, CA, USA
- 2012 IEEE International High Level Design Validation and Test Workshop, HLDVT 2012, Huntington Beach, CA, USA, November 9-10, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-2897-5
- Huy Nguyen, Michael S. Hsiao:
Sequential equivalence checking of hard instances with targeted inductive invariants and efficient filtering strategies. 1-8 - Melanie Diepenbeck, Mathias Soeken
, Daniel Große, Rolf Drechsler:
Behavior Driven Development for circuit design and verification. 9-16 - Hao Zheng, Andrew Price, Chris J. Myers:
Using decision diagrams to compactly represent the state space for explicit model checking. 17-24 - Freek Verbeek, Julien Schmaltz:
Automatic generation of deadlock detection algorithms for a family of microarchitecture description languages of communication fabrics. 25-32 - Ian G. Harris:
Automatic generation of Verilog bus transactors from natural language protocol specifications. 33-40 - Rainer Findenig, Thomas Leitner, Wolfgang Ecker:
Single-source hardware modeling of different abstraction levels with State Charts. 41-48 - Dogan Ulus, Alper Sen:
Using haloes in mixed-signal assertion based verification. 49-55 - An-Che Cheng, Chia-Chih Yen, Jing-Yang Jou:
A formal method to improve SystemVerilog functional coverage. 56-63 - Bijan Alizadeh, Masahiro Fujita:
A functional test generation technique for RTL datapaths. 64-70 - Kanad Basu, Prabhat Mishra, Priyadarsan Patra:
Constrained signal selection for post-silicon validation. 71-75 - Diego Braga, Franco Fummi, Graziano Pravadelli, Sara Vinco:
The strange pair: IP-XACT and univerCM to integrate heterogeneous embedded systems. 76-83 - Yu Bai, Jens Brandt, Klaus Schneider:
Monitoring distributed reactive systems. 84-91 - Olfat El-Mahi, Gabriela Nicolescu, Gilles Pesant, Giovanni Beltrame:
Embedded system verification through constraint-based scheduling. 92-95 - Simone Bronuzzi, Giuseppe Di Guglielmo, Franco Fummi, Graziano Pravadelli:
Accurate profiling of oracles for self-checking time-constrained embedded software. 96-99 - Masahiro Fujita:
Post-silicon verification and debugging with control flow traces and patchable hardware. 100-107 - Nicola Nicolici:
On-chip stimuli generation for post-silicon validation. 108-109 - Kyle Balston, Alan J. Hu, Steven J. E. Wilton, Amir Nahir:
Emulation in post-silicon validation: It's not just for functionality anymore. 110-117 - Weiwei Chen, Che-Wei Chang, Xu Han, Rainer Dömer:
Eliminating race conditions in system-level models by using parallel simulation infrastructure. 118-123 - Christoph Schumacher, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid:
Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators. 124-131 - Mahesh Nanjundappa, Anirudh M. Kaushik, Hiren D. Patel, Sandeep K. Shukla:
Accelerating SystemC simulations using GPUs. 132-139 - Romain Lemaire, Sébastien Thuries, Frédéric Heitzmann:
A flexible modeling environment for a NoC-based multicore architecture. 140-147 - Neil C. Audsley, Ian Gray, Andrea Acquaviva, Ralph Haines:
ToucHMore toolchain and system software for energy and variability customisation. 148-155 - Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Andrea Acquaviva:
Energy aware TLM platform simulation via RTL abstraction. 156-163 - Rolf Drechsler, Ian G. Harris, Robert Wille:
Generating formal system models from natural language descriptions. 164-165
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