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ORCID(IC)FPT 2022: Hong Kong
- International Conference on Field-Programmable Technology, (IC)FPT 2022, Hong Kong, December 5-9, 2022. IEEE 2022, ISBN 978-1-6654-5336-3
- Sultan Alqahtani, Yiqun Zhu, Qizhi Shi, Xiaolin Meng, Xinhua Wang
:
A Highly Customizable and Efficient Hardware Implementation for Parallel Matrix Inversion. 1-2 - Orégane Desrentes, Florent de Dinechin:
Using integer linear programming for correctly rounded multipartite architectures. 1-8 - Yusuke Inuma, Yuko Hara-Azumi:
Hardware SAT Solver-based Area-efficient Accelerator for Autonomous Driving. 1-4 - Boma A. Adhi, Carlos Cortes, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano:
Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage. 1-4 - Yu Qian, Xuegong Zhou, Hao Zhou, Lingli Wang:
Efficient Reinforcement Learning Framework for Automated Logic Synthesis Exploration. 1-6 - Kristiyan Manev, Joseph Powell, Kaspar Matas, Dirk Koch:
byteman: A Bitstream Manipulation Framework. 1-9 - Xuefei He, Jianyi Cheng, George A. Constantinides:
Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level Synthesis. 1-4 - Masahiro Nishimura, Yuta Imamura, Taito Manabe, Yuichiro Shibata:
FPGA implementation of HDR synthesis processing with image compression techniques. 1-2 - Ahmed Kamaleldin, Diana Göhringer:
An Agile Tile-based Platform for Adaptive Heterogeneous Many-Core Systems. 1-4 - Shangshang Yao, Liang Zhang:
Hardware-Efficient FPGA-Based Approximate Multipliers for Error-Tolerant Computing. 1-8 - Wei Zhang, Ray C. C. Cheung, Yun Liang, Hiroki Nakahara:
Message from the General Chair and Program Co-Chairs. 1 - Muhammad Ali, Diana Göhringer:
Application Specific Instruction-Set Processors for Machine Learning Applications. 1-4 - Soundarya Jayaraman, Bingyi Zhang, Viktor K. Prasanna:
Hypersort: High-performance Parallel Sorting on HBM-enabled FPGA. 1-11 - Rui Fang, Siyang Jiang, Hsi-Wen Chen, Wei Ding, Ming-Syan Chen:
Dual-Triangular QR Decomposition with Global Acceleration and Partially Q-Rotation Skipping. 1-4 - Yun Liang, Hiroki Nakahara, Wei Zhang, Fubing Mao, Ray C. C. Cheung:
Preface. i - Hayato Mori, Hayato Amano, Akinobu Mizutani, Eisuke Okazaki, Yuki Konno, Kohei Sada, Tomohiro Ono, Yuma Yoshimoto, Hakaru Tamukoh, Takeshi Ohkawa, Midori Sugaya:
Desgin and Implementation of ROS2-based Autonomous Tiny Robot Car with Integration of Multiple ROS2 FPGA Nodes. 1-4 - Kentaro Sano, Atsushi Koshiba, Takaaki Miyajima, Tomohiro Ueno:
ESSPER: Elastic and Scalable System for High-Performance Reconfigurable Computing with Software-bridged APIs. 1 - Chao Chen, Bruno da Silva, Jianqing Li, Chengyu Liu:
Acceleration of Fast Sample Entropy Towards Biomedical Applications on FPGAs. 1-4 - Hayden Cook, Jonathan Thompson, Zephram Tripp, Brad L. Hutchings, Jeffrey Goeders:
Cloning the Unclonable: Physically Cloning an FPGA Ring-Oscillator PUF. 1-10 - Bo Peng, Yuzhu Zhou, Qiang Li, Maosong Lin, Jiankui Weng, Qiang Zeng:
FPGA Implementation of Low-Latency Recursive Median Filter. 1-7 - Je Yang, Jaeuk Kim, Joo-Young Kim:
LearningGroup: A Real-Time Sparse Training on FPGA via Learnable Weight Grouping for Multi-Agent Reinforcement Learning. 1-9 - Zakary Nafziger, Martin Chua, Daniel Holanda Noronha, Steven J. E. Wilton:
Boosting Domain-Specific Debug Through Inter-frame Compression. 1-10 - Ryota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase:
Elastic Sample Filter: An FPGA-based Accelerator for Bayesian Network Structure Learning. 1 - Dongjoon Park, Yuanlong Xiao, André DeHon:
Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration. 1-10 - Mingyu Shu, Qiang Liu:
LCAM: Low-Cost Approximate Multiplier Design on FPGA. 1 - Ensieh Aliagha, Diana Göhringer:
Energy Efficient Design of Coarse-Grained Reconfigurable Architectures: Insights, Trends and Challenges. 1-11 - Yang Yang, Sanmukh R. Kuppannagari, Rajgopal Kannan, Viktor K. Prasanna:
Bandwidth Efficient Homomorphic Encrypted Matrix Vector Multiplication Accelerator on FPGA. 1-9 - Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar:
NetPU: Prototyping a Generic Reconfigurable Neural Network Accelerator Architecture. 1 - Abdullah T. Mughrabi, Gregory T. Byrd:
CAPI-Precis: Towards a Compute-Centric Interface for Coherent Shared Memory Accelerators. 1-9 - Qianfeng Clark Shen, Juan Camilo Vega, Paul Chow:
Parallel CRC On An FPGA At Terabit Speeds. 1-6 - Jiantao Liu, Carmine Rizzi, Lana Josipovic:
Load-Store Queue Sizing for Efficient Dataflow Circuits. 1-9 - Behnam Khaleghi, Tianqi Zhang, Cameron Martino, George Armstrong, Ameen Akel, Ken Curewitz, Justin Eno, Sean Eilert, Rob Knight, Niema Moshiri, Tajana Rosing:
SALIENT: Ultra-Fast FPGA-based Short Read Alignment. 1-10 - Mohamed A. Elgammal, Vaughn Betz:
Quality & Generality: A Flexible FPGA Re-Clustering Technique to Improve Packing and Placement. 1-2 - Kota Hisafuru, Ryotaro Negishi, Soma Kawakami, Dai Sato, Kazuki Yamashita, Keisuke Fukada, Nozomu Togawa:
Autonomous driving system with feature extraction using a binarized autoencoder. 1-4 - Jean-Michel Gorius, Simon Rokicki, Steven Derrien:
Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis. 1-6 - Michael Barrow, Zhuanhao Wu, Scott Lloyd, Maya B. Gokhale, Hiren D. Patel, Peter Lindstrom:
ZHW: A Numerical CODEC for Big Data Scientific Computation. 1-9 - Shikha Goel, Rajesh Kedia, Rijurekha Sen, M. Balakrishnan:
EXPRESS: CNN EXecution Time PREdiction for DPU DeSign Space Exploration. 1-2 - Ioanna Souvatzoglou, Dimitris Agiakatsikas, George Antonopoulos, Vasileios Vlagkoulis, Aitzan Sari, Athanasios Papadimitriou, Mihalis Psarakis:
The Impact of Hardware Folding on Dependability in Spaceborne FPGA-based Neural Networks. 1 - Marius Stan, Mathew Hall, Mohamed Ibrahim, Vaughn Betz:
HPIPE NX: Boosting CNN Inference Acceleration Performance with AI-Optimized FPGAs. 1-9 - Mariko Tatsumi, Silviu-Ioan Filip, Caroline White, Olivier Sentieys, Guy Lemieux:
Mixing Low-Precision Formats in Multiply-Accumulate Units for DNN Training. 1-9 - Saeid Gorgin, MohammadHosein Gholamrezaei, Danial Javaheri, Jeong-A Lee:
An Energy-Efficient K-means Clustering FPGA Accelerator via Most-Significant Digit First Arithmetic. 1-4 - Katsuaki Kamimae, Shintaro Matsui, Yasutoshi Araki, Takehiro Miura, Keigo Motoyoshi, Keizo Yamashita, Haruto Ikehara, Takuho Kawazu, Huang Yuwei, Masahiro Nishimura, Shuto Abe, Kenyu Okino, Yuta Hashiguchi, Koki Fukuda, Kengo Yanagihara, Taito Manabe, Yuichiro Shibata:
A Lane Detection Hardware Algorithm Based on Helmholtz Principle and Its Application to Unmanned Mobile Vehicles. 1-4 - Xu Zhang, Yisong Chang, Tianyue Lu, Ke Liu, Ke Zhang, Mingyu Chen:
GraFF: A Multi-FPGA System with Memory Semantic Fabric for Scalable Graph Processing. 1-2 - Yukui Luo, Yuheng Zhang, Shijin Duan, Xiaolin Xu:
A Cautionary Note on Building Multi-tenant Cloud-FPGA as a Secure Infrastructure. 1-6 - Reilly McKendrick, Corey Simpson, Brent Nelson, Jeffrey Goeders:
Leveraging FPGA Primitives to Improve Word Reconstruction during Netlist Reverse Engineering. 1-5 - Vibhakar Vemulapati, Deming Chen:
FSLAM: an Efficient and Accurate SLAM Accelerator on SoC FPGAs. 1-9 - Zhongpei Liu, Gaofeng Lv, Jichang Wang, Xiangrui Yang:
Memory-efficient RMT Matching Optimization Based on MBitTree. 1-9 - Filip Wojcicki, Zhiqiang Que, Alexander D. Tapper, Wayne Luk:
Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments. 1-8 - Trishna Rajkumar, Johnny Öberg:
A Markovian Approach for Detecting Failures in the Xilinx SEM core. 1-4 - Dongdong Tang, Xuan Sun, Nan Guan, Tei-Wei Kuo, Chun Jason Xue:
$p$LPAQ: Accelerating LPAQ Compression on FPGA. 1-6 - Nobuho Hashimoto, Shinya Takamaeda-Yamazaki:
FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design. 1-9 - Akira Kojima:
Implementation and Improvement of Autonomous Robot Car using SoC FPGA with DPU. 1-4 - Ariel Podlubne, Diana Göhringer:
Modeling FPGA-based Architectures for Robotics. 1-4 - Kaspar Mätas, Kristiyan Manev, Joseph Powell, Dirk Koch:
Automated Generation and Orchestration of Stream Processing Pipelines on FPGAs. 1-10 - Shashwat Khandelwal, Shanker Shreejith:
A Lightweight FPGA-based IDS-ECU Architecture for Automotive CAN. 1-9 - Tendayi Kamucheka, Alexander Nelson, David Andrews, Miaoqing Huang:
A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm. 1 - Keisuke Sugiura, Hiroki Matsutani:
P3Net: PointNet-based Path Planning on FPGA. 1-9
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