default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID25. FPGA 2017: Monterey, CA, USA
- Jonathan W. Greene, Jason Helge Anderson:
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2017, Monterey, CA, USA, February 22-24, 2017. ACM 2017, ISBN 978-1-4503-4354-1
FPGA'17 Workshops
- Hayden Kwok-Hay So, John Wawrzynek:
OLAF'17: Third International Workshop on Overlay Architectures for FPGAs. 1
Special Session: The Role of FPGAs in Deep Learning
- Andrew Ling, Jason Anderson:
The Role of FPGAs in Deep Learning. 3 - Eriko Nurvitadhi, Ganesh Venkatesh, Jaewoong Sim, Debbie Marr, Randy Huang, Jason Ong Gee Hock, Yeong Tat Liew, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra, Guy Boudoukh:
Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? 5-14 - Ritchie Zhao, Weinan Song, Wentao Zhang, Tianwei Xing, Jeng-Hau Lin, Mani B. Srivastava, Rajesh Gupta, Zhiru Zhang:
Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs. 15-24 - Jialiang Zhang, Jing Li:
Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network. 25-34 - Chi Zhang, Viktor K. Prasanna:
Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory System. 35-44 - Yufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo:
Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks. 45-54
Machine Learning
- Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu:
An OpenCL™ Deep Learning Accelerator on Arria 10. 55-64 - Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers:
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference. 65-74 - Song Han, Junlong Kang, Huizi Mao, Yiming Hu, Xin Li, Yubin Li, Dongliang Xie, Hong Luo, Song Yao, Yu Wang, Huazhong Yang, William (Bill) J. Dally:
ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGA. 75-84
Interconnect and Routing
- Hans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon:
Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delays. 85-94 - Alex Rodionov, Jonathan Rose:
Synchronization Constraints for Interconnect Synthesis. 95-104 - Minghua Shen, Guojie Luo:
Corolla: GPU-Accelerated FPGA Routing Based on Subgraph Dynamic Expansion. 105-114
Architecture
- Sadegh Yazdanshenas, Kosuke Tatsumura, Vaughn Betz:
Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration. 115-124 - Hsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, Joel S. Emer:
Automatic Construction of Program-Optimized FPGA Memory Networks. 125-134 - Zhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang:
NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element. 135-140 - Chethan Kumar H. B, Prashant Ravi, Gourav Modi, Nachiket Kapre:
120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA board. 141-146
CAD Tools
- Gai Liu, Zhiru Zhang:
A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping. 147-156 - Chang Xu, Gai Liu, Ritchie Zhao, Stephen Yang, Guojie Luo, Zhiru Zhang:
A Parallel Bandit-Based Approach for Autotuning FPGA Compilation. 157-166
Panel: FPGAs in the Cloud
- George A. Constantinides:
FPGAs in the Cloud. 167
High-Level Synthesis -- Tools and Applications
- Nadesh Ramanathan, Shane T. Fleming, John Wickerson, George A. Constantinides:
Hardware Synthesis of Weakly Consistent C Concurrency. 169-178 - Yuan Zhou, Khalid Musa Al-Hawaj, Zhiru Zhang:
A New Approach to Automatic Memory Banking using Trace-Based Address Mining. 179-188 - Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang:
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. 189-194 - Nitish Kumar Srivastava, Steve Dai, Rajit Manohar, Zhiru Zhang:
Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. 195-200 - Daniel Rozhko, Geoffrey Elliott, Daniel Ly-Ma, Paul Chow, Hans-Arno Jacobsen:
Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules. 201-206
Graph Processing Applications
- Jialiang Zhang, Soroosh Khoram, Jing Li:
Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First Search. 207-216 - Guohao Dai, Tianhao Huang, Yuze Chi, Ningyi Xu, Yu Wang, Huazhong Yang:
ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture. 217-226 - Xiaoyu Ma, Dan Zhang, Derek Chiou:
FPGA-Accelerated Transactional Execution of Graph Workloads. 227-236
Virtualization and Applications
- Naif Tarafdar, Thomas Lin, Eric Fukuda, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow:
Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center. 237-246 - Dennis Weller, Fabian Oboril, Dimitar Lukarski, Jürgen Becker, Mehdi Baradaran Tahoori:
Energy Efficient Scientific Computing on FPGAs using OpenCL. 247-256 - Xin Fang, Stratis Ioannidis, Miriam Leeser:
Secure Function Evaluation Using an FPGA Overlay Architecture. 257-266
Applications
- Zhuolun He, Guojie Luo:
FPGA Acceleration for Computational Glass-Free Displays. 267-274 - Sitao Huang, Gowthami Jayashri Manikandan, Anand Ramachandran, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen:
Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant Calling. 275-284
Poster Session 1
- Andy Gean Ye, Karthik Ganesan:
Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only). 285 - Yue Zha, Jialiang Zhang, Zhiqiang Wei, Jing Li:
A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only). 285 - Shuo Wang, Yun Liang:
A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from OpenCL Programming Model (Abstract Only). 285-286 - Yanqiang Liu, Yao Li, Weilun Xiong, Meng Lai, Cheng Chen, Zhengwei Qi, Haibing Guan:
Scala Based FPGA Design Flow (Abstract Only). 286 - Girish Deshpande, Dinesh K. Bhatia:
Thermal Flattening in 3D FPGAs Using Embedded Cooling (Abstract Only). 286 - Gary William Grewal, Shawki Areibi, Matthew Westrik, Ziad Abuowaimer, Betty Zhao:
A Machine Learning Framework for FPGA Placement (Abstract Only). 286 - Ralf Salomon, Ralf Joost:
Precise Coincidence Detection on FPGAs: Three Case Studies (Abstract Only). 287 - Mostafa Koraei, Magnus Jahre, S. Omid Fatemi:
Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC Applications (Abstract Only). 287 - Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet:
Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only). 287 - Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois:
An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only). 287-288
Poster Session 2
- Zhipeng Zhao, James C. Hoe:
Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only). 289 - Christophe Bobda, Taylor J. L. Whitaker, Charles A. Kamhoua, Kevin A. Kwiat, Laurent Njilla:
Automatic Generation of Hardware Sandboxes for Trojan Mitigation in Systems on Chip (Abstract Only). 289 - Haohuan Fu, Conghui He, Huabin Ruan, Itay Greenspon, Wayne Luk, Yongkang Zheng, Junfeng Liao, Qing Zhang, Guangwen Yang:
Accelerating Financial Market Server through Hybrid List Design (Abstract Only). 289-290 - Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei:
Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). 290 - Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura:
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). 290 - Yixing Li, Zichuan Liu, Kai Xu, Hao Yu, Fengbo Ren:
A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only). 290-291 - Jason Cong, Zhenman Fang, Muhuan Huang, Libo Wang, Di Wu:
CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only). 291 - Mohammed Alawad, Mingjie Lin:
Stochastic-Based Multi-stage Streaming Realization of a Deep Convolutional Neural Network (Abstract Only). 291 - Stylianos I. Venieris, Christos-Savvas Bouganis:
fpgaConvNet: Automated Mapping of Convolutional Neural Networks on FPGAs (Abstract Only). 291-292
Poster Session 3
- Emanuele Pezzotti, Alex Iacobucci, Gregory Nash, Umer I. Cheema, Paolo Vinella, Rashid Ansari:
FPGA-based Hardware Accelerator for Image Reconstruction in Magnetic Resonance Imaging (Abstract Only). 293 - Yongming Shen, Michael Ferdman, Peter A. Milder:
Storage-Efficient Batching for Minimizing Bandwidth of Fully-Connected Neural Network Layers (Abstract Only). 293 - Subho S. Banerjee, Mohamed El-Hadedy, Jong Bin Lim, Daniel Chen, Zbigniew T. Kalbarczyk, Deming Chen, Ravishankar K. Iyer:
ASAP: Accelerated Short Read Alignment on Programmable Hardware (Abstract Only). 293-294 - Atieh Lotfi, Rajesh K. Gupta:
RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only). 294 - Haoyang Wu, Tao Wang, Zhiwei Li, Boyan Ding, Xiaoguang Li, Tianfu Jiang, Jun Liu, Songwu Lu:
GRT 2.0: An FPGA-based SDR Platform for Cognitive Radio Networks (Abstract Only). 294-295 - Srinivas Siripurapu, Aman Gayasen, Padmini Gopalakrishnan, Nitin Chandrachoodan:
FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only). 295 - Shouyi Yin, Dajiang Liu, Lifeng Sun, Xinhan Lin, Leibo Liu, Shaojun Wei:
Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only). 295 - Sumanta Chaudhuri:
Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only). 295-296 - Fubing Mao, Wei Zhang, Bingsheng He, SiewKei Lam:
Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only). 296 - Wei Ting Loke, Chin Yang Koay:
An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation (Abstract Only). 296
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-08 20:17 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
