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ORCID23rd FCCM 2015: Vancouver, BC, Canada
- 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2015, Vancouver, BC, Canada, May 2-6, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-9969-9
Trends, Revisits, and Overlays
- Lesley Shannon, Veronica Cojocaru, Cong Nguyen Dao, Philip Heng Wai Leong
:
Technology Scaling in FPGAs: Trends in Applications and Architectures. 1-8 - Aaron Landy, Greg Stitt:
Revisiting Serial Arithmetic: A Performance and Tradeoff Analysis for Parallel Applications on Modern FPGAs. 9-16 - Michael Xi Yue, Dirk Koch, Guy G. F. Lemieux:
Rapid Overlay Builder for Xilinx FPGAs. 17-20 - James Coole, Greg Stitt:
Adjustable-Cost Overlays for Runtime Compilation. 21-24 - Abhishek Kumar Jain, Suhaib A. Fahmy, Douglas L. Maskell:
Efficient Overlay Architecture Based on DSP Blocks. 25-28
Poster Session I
- Mohamed W. Hassan, Ahmed E. Helal, Yasser Y. Hanafy:
High Performance Sparse LU Solver FPGA Accelerator Using a Static Synchronous Data Flow Model. 29 - Sunil Shukla, David F. Bacon:
Cycle-Accurate Replay and Debugging of Running FPGA Systems. 30 - Santhosh Kumar Rethinagiri, Oscar Palomar, Javier Arias Moreno, Osman S. Unsal, Adrián Cristal:
Heterogeneous Platform to Accelerate Compute Intensive Applications. 31 - Matthias Göbel, Chi Ching Chi, Mauricio Alvarez-Mesa, Ben H. H. Juurlink:
High Performance Memory Accesses on FPGA-SoCs: A Quantitative Analysis. 32 - Nachiket Kapre:
Sparse Graph Processing with Soft-Processors. 33 - Ze-ke Wang, Bingsheng He, Wei Zhang:
Improving Data Partitioning Performance on OpenCL-Based FPGAs. 34 - Hongyuan Ding, Miaoqing Huang:
Performance and Energy Optimization on MPSoCs by Enabling STT-MRAM LUTs. 35
Networking and Compression
- David Sidler, Gustavo Alonso, Michaela Blott, Kimon Karras, Kees A. Vissers, Raymond Carley:
Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware. 36-43 - Yun Rock Qu, Viktor K. Prasanna:
Enabling High Throughput and Virtualization for Traffic Classification on FPGA. 44-51 - Jeremy Fowers, Joo-Young Kim, Doug Burger, Scott Hauck:
A Scalable High-Bandwidth Architecture for Lossless Compression on FPGAs. 52-59 - Thiem Van Chu, Shimpei Sato, Kenji Kise:
Enabling Fast and Accurate Emulation of Large-Scale Network on Chip Architectures on a Single FPGA. 60-63 - Paul Grigoras, Pavel Burovskiy, Eddie Hung, Wayne Luk:
Accelerating SpMV on FPGAs by Compressing Nonzero Values. 64-67
Power and Energy
- Pradeep Moorthy, Nachiket Kapre:
Zedwulf: Power-Performance Tradeoffs of a 32-Node Zynq SoC Cluster. 68-75 - Gopalakrishna Hegde, Nachiket Kapre:
Energy-Efficient Acceleration of OpenCV Saliency Computation Using Soft Vector Processors. 76-83 - Azamat Mametjanov, Prasanna Balaprakash, Chekuri Choudary, Paul D. Hovland, Stefan M. Wild, Gerald Sabin:
Autotuning FPGA Design Parameters for Performance and Power. 84-91 - Mohammed Alawad, Mingjie Lin:
FIR Filter Based on Stochastic Computing with Reconfigurable Digital Fabric. 92-95
Poster Session II
- Mohsen Ghasempour, Jonathan Heathcote, Javier Navaridas, Luis A. Plana, Jim D. Garside, Mikel Luján:
Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study. 96 - João Andrade, Nithin George, Kimon Karras, David Novo, Vítor Manuel Mendes da Silva, Paolo Ienne, Gabriel Falcão Paiva Fernandes:
Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders. 97 - Bo Peng, Xi Jin, Tianqi Wang, Xueliang Du:
Design of a Distributed Compressor for Astronomy SSD. 98 - John W. Lockwood:
Scalable Key/Value Search in Datacenters. 99 - Marco Minutoli, Vito Giovanni Castellana, Antonino Tumeo, Fabrizio Ferrandi:
Function Proxies for Improved Resource Sharing in High Level Synthesis. 100 - Cheng Liu, Hayden Kwok-Hay So:
Automatic Soft CGRA Overlay Customization for High-Productivity Nested Loop Acceleration on FPGAs. 101 - Jeevan Sirkunan, Chia Yee Ooi, Muhammad N. Shaikh-Husin, Yuan Wen Hau, Muhammad N. Marsono:
Adaptive Configurable Transactional Memory for Multi-processor FPGA Platforms. 102
Machine Learning Techniques
- Liucheng Guo, Ce Guo, David B. Thomas, Wayne Luk:
Pipelined Genetic Propagation. 103-110 - Sicheng Li, Chunpeng Wu, Hai Li, Boxun Li, Yu Wang, Qinru Qiu:
FPGA Acceleration of Recurrent Neural Network Based Language Model. 111-118 - Nachiket Kapre, Bibin Chandrashekaran, Harnhua Ng, Kirvy Teo:
Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing. 119-126
Debug, Test, and Fault Detection
- Jeffrey B. Goeders, Steven J. E. Wilton:
Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAs. 127-134 - Oriol Arcas-Abella, Adrián Cristal, Osman S. Unsal:
High-Level Debugging and Verification for FPGA-Based Multicore Architectures. 135-142 - Nathan A. Harward, Michael R. Gardiner, Luke W. Hsiao, Michael J. Wirthlin:
Estimating Soft Processor Soft Error Sensitivity through Fault Injection. 143-150 - Pawel Swierczynski, Marc Fyrbiak, Christof Paar, Christophe Huriaux, Russell Tessier:
Protecting against Cryptographic Trojans in FPGAs. 151-154 - Alban Bourge, Olivier Muller, Frédéric Rousseau:
Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems. 155-158 - Junyi Liu, Samuel Bayliss, George A. Constantinides:
Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS. 159-162
Poster Session III
- Behzad Salami, Oriol Arcas-Abella, Nehir Sönmez:
HATCH: Hash Table Caching in Hardware for Efficient Relational Join on FPGA. 163 - Katayoun Neshatpour, Maria Malik, Mohammad Ali Ghodrat, Houman Homayoun:
Accelerating Big Data Analytics Using FPGAs. 164 - Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser:
Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System. 165 - Luca Bochi Saldanha, Christophe Bobda:
A System on Reconfigurable Chip for Handwritten Digit Recognition. 166 - Yuliang Pu, Jun Peng, Letian Huang, John Chen:
An Efficient KNN Algorithm Implemented on FPGA Based Heterogeneous Computing System Using OpenCL. 167-170
Applications
- Francis P. Russell, Peter D. Düben, Xinyu Niu, Wayne Luk, Tim N. Palmer:
Architectures and Precision Analysis for Modelling Atmospheric Variables with Chaotic Behaviour. 171-178 - Roger Moussalli, Mudhakar Srivatsa, Sameh W. Asaad:
Fast and Flexible Conversion of Geohash Codes to and from Latitude/Longitude Coordinates. 179-186 - Bita Darvish Rouhani, Ebrahim M. Songhori, Azalia Mirhoseini, Farinaz Koushanfar:
SSketch: An Automated Framework for Streaming Sketch-Based Analysis of Big Data on FPGA. 187-194 - Jens Korinth, David de la Chevallerie, Andreas Koch:
An Open-Source Tool Flow for the Composition of Reconfigurable Hardware Thread Pool Architectures. 195-198 - Yu-Ting Chen, Jason Cong, Jie Lei, Peng Wei:
A Novel High-Throughput Acceleration Engine for Read Alignment. 199-202 - Dongyang Li, Qing Yang, Qingbo Wang, Cyril Guyot, Ashwin Narasimha, Dejan Vucinic, Zvonimir Bandic:
A Parallel and Pipelined Architecture for Accelerating Fingerprint Computation in High Throughput Data Storages. 203-206
Implementation I
- Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
Modular SRAM-Based Binary Content-Addressable Memories. 207-214 - Christopher W. Fletcher, Ling Ren, Albert Kwon, Marten van Dijk, Emil Stefanov, Dimitrios N. Serpanos, Srinivas Devadas:
A Low-Latency, Low-Area Hardware Oblivious RAM Controller. 215-222 - Farheen Fatima Khan, Andy Ye:
Measuring the Accuracy of Minimum Width Transistor Area in Estimating FPGA Layout Area. 223-226 - Aaron Wood, Scott Hauck:
Offset Pipelined Scheduling: Conditional Branching for CGRAs. 227-230
Poster Session IV
- Xabier Iturbe, Didier Keymeulen, Patrick Yiu, Dan Berisford, Kevin P. Hand, Robert Carlson, Emre Ozer:
A Highly-Efficient, Adaptive and Fault-Tolerant SoC Implementation of a Fourier Transform Spectrometer Data Processing. 231 - Yuteng Zhou, Wei Wang, Xinming Huang:
FPGA Design for PCANet Deep Learning Network. 232 - Brice Colombier, Lilian Bossuet:
Functional Locking Modules for Design Protection of Intellectual Property Cores. 233 - Alireza Monemi, Chia Yee Ooi, Muhammad Nadzir Marsono:
Virtual Channel and Switch Allocation for Low Latency Network-on-Chip Routers. 234 - Carlos Rodriguez-Donate, Guillermo Botella, Carlos García, Eduardo Cabal-Yepez, Manuel Prieto-Matías:
Early Experiences with OpenCL on FPGAs: Convolution Case Study. 235
Implementation II
- Bangtian Liu, Haohuan Fu, Lin Gan, Wenlai Zhao, Guangwen Yang:
Optimizing Residue Number Reverse Converters through Bitwise Arithmetic on FPGAs. 236-243 - Jason Kane, Robert Hernandez, Qing Yang:
A Reconfigurable Multiclass Support Vector Machine Architecture for Real-Time Embedded Systems Classification. 244-251 - Marco Rabozzi, Antonio Miele, Marco D. Santambrogio:
Floorplanning for Partially-Reconfigurable FPGAs via Feasible Placements Detection. 252-255 - Victor M. Goncalves Martins, Joao Gabriel Reis, Horácio C. Neto, Eduardo Augusto Bezerra:
Designing Partial Bitstreams for Multiple Xilinx FPGA Partitions. 256-259
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