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ORCIDEWDTS 2008: Lviv, Ukraine
- 2008 East-West Design & Test Symposium, EWDTS 2008, Lviv, Ukraine, October 9-12, 2008. IEEE Computer Society 2008, ISBN 978-1-4244-3402-2
- Franco Fummi, Valerio Guarnieri, Cristina Marconcini, Graziano Pravadelli
:
An optimized CLP-based technique for generating propagation sequences. 25-29 - Tom English, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens:
HotSpot: Visualizing dynamic power consumption in RTL designs. 45-48 - Andrzej Wielgus, Witold A. Pleskacz:
Characterization of CMOS sequential standard cells for defect based voltage testing. 49-54 - Slawomir Zielski, Janusz Sosnowski:
Testing the control part of peripheral interfaces. 55-58 - Grzegorz Labiak, Marian Adamski:
Concurrent processes synchronisation in statecharts for FPGA implementation. 59-64 - Alexander Kamkin:
Coverage-directed verification of microprocessor units based on cycle-accurate contract specifications. 84-87 - Dmytro Lazorenko:
Multidimensional loop fusion for low-power. 92-95 - Nadereh Hatami, Zainalabedin Navabi:
An advanced method for synthesizing TLM2-based interfaces. 104-108 - Andrey Ayupov, Leonid Kraginskiy:
A novel timing-driven placement algorithm using smooth timing analysis. 137-140 - Vazgen Melikyan, Aristakes Hovsepyan, Mkrtich Ishkhanyan, Tigran Hakobyan:
Digital lock detector for PLL. 141-142 - Vladimir Hahanov, Eugenia Litvinova, Karina Krasnoyaruzhskaya, Sergey Galagan:
Diagnosis of SoC faulty memory cells for embedded repair. 143-148 - Svetlana Chumachenko, Wajeb Gharibi, Anna Hahanova, Aleksey Sushanov:
SoC software components diagnosis technology. 155-158 - Vladimir Hahanov, Olesya Guz, Natalya Kulbakova, Maxim Davydov:
Vector-logical diagnosis method for SOC functionalities. 159-162 - Maryna Kaminska, Roman Prikhodchenko, Artem Kubirya, Pavel Mocar:
Testability analysis method for hardware and software based on assertion libraries. 163-167 - Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi:
An IEEE 1500 compatible wrapper architecture for testing cores at transaction level. 178-181 - Negin Mahani, Parnian Mokri, Zainalabedin Navabi:
System level hardware design and simulation with SystemAda. 190-193 - Somayeh Malekshahi, Mahshid Sedghi, Zainalabedin Navabi:
Automating Hardware/Software partitioning using dependency Graph. 196-199 - Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Mahmood Fathy, Zainalabedin Navabi:
Reliable NoC architecture utilizing a robust rerouting algorithm. 200-203 - Alexander V. Drozd, Svetlana Antoshchuk, Andrzej Rucinski, A. Martinuk:
Parity prediction method for on-line testing of a Barrel-shifter. 208-215 - Nicola Bombieri, Franco Fummi, Graziano Pravadelli:
RTL-TLM equivalence checking based on simulation. 214-217 - Sergiy Boroday, Alexandre Petrenko, Andreas Ulrich:
Test suite consistency verification. 235-239 - Najmeh Farajipour, S. Behdad Hosseini, Zainalabedin Navabi:
Utilizing HDL simulation engines for accelerating design and test processes. 371-375 - Nasim Kazemifard, Maryam Ebrahimpour, Mostafa Rahimi Azghadi, Mohammad A. Tehrani, Keivan Navi:
Performance evaluation of In-Circuit Testing on QCA based circuits. 375-378 - Bikram Garg, Ashish Agrawal, Rajeev Sehgal, Amarpal Singh, Manish Khanna:
Partitioning, floor planning, detailed placement and routing techniques for schematic generation of analog netlist. 379-382 - Andrei Karatkevich:
On macroplaces in Petri nets. 418-422
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