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ORCIDETW 2000: Cascais, Portugal
- 5th European Test Workshop, ETW 2000, Cascais, Portugal, May 23-26, 2000. IEEE Computer Society 2000, ISBN 0-7695-0701-8
- Han Speek, Hans G. Kerkhoff, Manoj Sachdev, Mansour Shashaani:
Bridging the testing speed gap: design for delay testability. 3-8 - Arnaud Virazel
, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch:
Delay fault testing: choosing between random SIC and random MIC test sequences. 9-14 - Andrew Burdass, Gary Campbell, Richard Grisenthwaite, David Gwilt, Peter Harrod, Richard York:
Microprocessor cores. 17-22 - Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno:
System-level test bench generation in a co-design framework. 25-30 - Antoni Ferré, Joan Figueras:
LEAP: An accurate defect-free IDDQ estimator. 33-38 - Masaru Sanada:
Defect detection from visual abnormalities in manufacturing process using IDDQ. 39-44 - Daniela De Venuto, Michael J. Ohletz, G. Matarrese:
Static and dynamic on-chip test response evaluation using a two-mode comparator. 47-52 - Florence Azaïs, Serge Bernard, Y. Betrand, Michel Renovell:
Towards an ADC BIST scheme using the histogram test technique. 53-58 - Piet Engelke, Bernd Becker, Martin Keim:
A parameterizable fault simulator for bridging faults. 63-68 - Mykola Blyzniuk, T. Cibáková, Elena Gramatová, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar:
Hierarchical defect-oriented fault simulation for digital circuits. 69-74 - Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian:
Analyzing the test generation problem for an application-oriented test of FPGAs. 75-80 - Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche:
Test challenges in nanometer technologies. 83-90 - Anton Chichkov, Dirk Merlier, Peter Cox:
Current testing procedure for deep submicron devices. 91-96 - Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira:
RTL-based functional test generation for high defects coverage in digital SOCs. 99-104 - Marco Boschini, Xiaoming Yu, Franco Fummi, Elizabeth M. Rudnick:
Combining symbolic and genetic techniques for efficient sequential circuit test generation. 105-110 - Yiorgos Makris, Jamison Collins, Alex Orailoglu:
How to avoid random walks in hierarchical test path identification. 111-116 - Monica Lobetti Bodoni, Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
An effective distributed BIST architecture for RAMs. 119-124 - Jörg E. Vollrath, Ulf Lederer, Thomas Hladschik:
Compressed bit fail maps for memory fail pattern classification. 125-130 - David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre:
A method for trading off test time, area and fault coverage in datapath BIST synthesis. 133-139 - Ismet Bayraktaroglu, Alex Orailoglu:
Low cost concurrent test implementation for linear digital systems. 140-143 - Irith Pomeranz, Sudhakar M. Reddy:
On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits. 144-149 - Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva:
A system level boundary scan controller board for VME applications [to CERN experiments]. 153-158 - Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof:
Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path. 161-166 - Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante:
CA-CSTP: a new BIST architecture for sequential circuits. 167-172 - Bram Kruseman:
Comparison of defect detection capabilities of current-based and voltage-based test methods. 175-180
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