default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDETS 2008: Verbania, Italy
- 13th European Test Symposium, ETS 2008, Verbania, Italy, May 25-29, 2008. IEEE Computer Society 2008, ISBN 978-0-7695-3150-2
Keynote Presentations
- Antonio Rubio:
The Role of Test in Circuits Built with Unreliable Components. 3 - Thomas W. Williams:
The Future Is Low Power and Test. 4
Testing and Monitoring for High Quality Requirements
- Irith Pomeranz, Sudhakar M. Reddy:
Safe Fault Collapsing Based on Dominance Relations. 7-12 - Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre:
A Reliable Architecture for the Advanced Encryption Standard. 13-18
SoC Infrastructure
- Ardy van den Berg, Pengwei Ren, Erik Jan Marinissen
, Georgi Gaydadjiev, Kees Goossens:
Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism. 21-26 - Vladimir A. Zivkovic, Frank van der Heyden, Guido Gronthoud, Frans G. M. de Jong:
Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design. 27-32
Advances in RF Testing
- Nathan Kupp, Petros Drineas, Mustapha Slamani, Yiorgos Makris:
Confidence Estimation in Non-RF to RF Correlation-Based Specification Test Compaction. 35-40 - Rajarajan Senguttuvan, Hyun Woo Choi, Donghoon Han, Abhijit Chatterjee:
Built-in Test of Frequency Modulated RF Transmitters Using Embedded Low-Pass Filters. 41-46 - Eduardo Aldrete-Vidrio, M. Amine Salhi, Josep Altet, Stéphane Grauby, Diego Mateo, H. Michel, L. Clerjaud, Jean-Michel Rampnoux, Antonio Rubio, Wilfrid Claeys, Stefan Dilhaire:
Using Temperature as Observable of the Frequency Response of RF CMOS Amplifiers. 47-52
Safe Test Generation and Design Validation
- Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja:
A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. 55-60 - Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar:
Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. 61-68 - Ehab Anis Daoud, Nicola Nicolici:
On Bypassing Blocking Bugs during Post-Silicon Validation. 69-74
News from Memory Test
- Simone Alpe, Stefano Di Carlo, Paolo Prinetto, Alessandro Savino:
Applying March Tests to K-Way Set-Associative Cache Memories. 77-83 - Benoît Godard, Jean Michel Daga, Lionel Torres, Gilles Sassatelli:
Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories. 84-90 - Swapnil Bahl, Vishal Srivastava:
Self-Programmable Shared BIST for Testing Multiple Memories. 91-96
Diagnosis: New Concepts and Industrial Application
- S. Saqib Khursheed, Paul M. Rosinger, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod:
Bridge Defect Diagnosis for Multiple-Voltage Design. 99-104 - Yu Huang, Wu-Tung Cheng, Ruifeng Guo:
Diagnose Multiple Stuck-at Scan Chain Faults. 105-110
Delay Faults: Simulation, Test Generation and DFT
- Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker:
A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. 113-118 - Rajeshwary Tayade, Jacob A. Abraham:
Critical Path Selection for Delay Test Considering Coupling Noise. 119-124 - Seongmoon Wang, Wenlong Wei:
Low Overhead Partial Enhanced Scan Technique for Compact and High Fault Coverage Transition Delay Test Patterns. 125-130
SoC Testing
- Martin Hilscher, Michael Braun, Michael Richter, Andreas Leininger, Michael Gössel:
Accelerated Shift Registers for X-tolerant Test Data Compaction. 133-139 - Davide Appello, Paolo Bernardi, R. Cagliesi, M. Giancarlini, Michelangelo Grosso:
An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs. 140-145
On-Chip Resources for Mixed-Signal Devices
- Esa Korhonen, Juha Kostamovaara:
An Improved Algorithm to Identify the Test Stimulus in Histogram-Based A/D Converter Testing. 149-154
Solutions for Yield Enhancement
- Qingqi Dou, Jacob A. Abraham:
Jitter Decomposition in High-Speed Communication Systems. 157-162
On-Line Checking
- Daniele Rossi, Paolo Angelini, Cecilia Metra, Giovanni Campardo, Gian Pietro Vanalli:
Risks for Signal Integrity in System in Package and Possible Remedies. 165-170 - Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche:
Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic. 171-176
Soft Error Mitigation
- Quming Zhou, Mihir R. Choudhury, Kartik Mohanram:
Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits. 179-184 - Christian G. Zoellin, Hans-Joachim Wunderlich, Ilia Polian, Bernd Becker:
Selective Hardening in Early Design Steps. 185-190 - Laura Frigerio, Matteo Alan Radaelli, Fabio Salice:
Convolutional Coding for SEU mitigation. 191-196
ETS07 Best Paper
- Stefan Holst, Hans-Joachim Wunderlich:
Adaptive Debug and Diagnosis without Fault Dictionaries. 199-204
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-01-03 23:17 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
