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ORCIDETS 2005: Tallinn, Estonia
- 10th European Test Symposium, ETS 2005, Tallinn, Estonia, May 22-25, 2005. IEEE Computer Society 2005, ISBN 0-7695-2341-2
- Raimund Ubar
, Tatjana Shchenova, Gert Jervan, Zebo Peng:
Energy minimization for hybrid BIST in a system-on-chip test environment. 2-7 - Urban Ingelsson, Sandeep Kumar Goel, Erik Larsson, Erik Jan Marinissen:
Test scheduling for modular SOCs in an abort-on-fail environment. 8-13 - Dan Zhao, Shambhu J. Upadhyaya, Martin Margala:
A new SoC test architecture with RF/wireless connectivity. 14-19 - Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker:
A unified fault model and test generation procedure for interconnect opens and bridges. 22-27 - Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras:
Defective behaviours of resistive opens in interconnect lines. 28-33 - Víctor H. Champac, Antonio Zenteno, José L. Garcia:
Testing of resistive opens in CMOS latches and flip-flops. 34-40 - Irith Pomeranz, Sudhakar M. Reddy:
Using dummy bridging faults to define a reduced set of target faults. 42-47 - Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation. 48-53 - Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
Path-oriented transition fault test generation considering operating conditions. 54-59 - Amir Zjajo, José Pineda de Gyvez:
Evaluation of signature-based testing of RF/analog circuits. 62-67 - Ganesh Srinivasan, Sasikumar Cherubal, Pramodchandran N. Variyam, Melese Teklu, C. P. Wang, David Guidry, Abhijit Chatterjee:
Accurate measurement of multi-tone power ratio (MTPR) of ADSL devices using low cost testers. 68-73 - Frédérick Mailly, Florence Azaïs, Norbert Dumas, Laurent Latorre, Pascal Nouet:
Towards on-line testing of MEMS using electro-thermal excitation. 76-81 - Achraf Dhayni, Salvador Mir, Libor Rufer:
Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities. 82-87 - Carl Jeffrey, Zhou Xu, Andrew Richardson:
Bias Superposition - An On-Line Test Strategy for a MEMS Based Conductivity Sensor. 88-93 - Jaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold A. Pleskacz:
DOT: new deterministic defect-oriented ATPG tool. 96-101 - Smita Krishnaswamy, Igor L. Markov, John P. Hayes:
Logic circuit testing for transient faults. 102-107 - Arijit Raychowdhury, Swaroop Ghosh, Swarup Bhunia, Debjyoti Ghosh, Kaushik Roy:
A novel delay fault testing methodology using on-chip low-overhead delay measurement hardware at strategic probe points. 108-113 - Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan:
Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. 116-121 - Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
Automatic March tests generation for static and dynamic faults in SRAMs. 122-127 - Matthew Collins, Bashir M. Al-Hashimi, J. Neil Ross:
A programmable time measurement architecture for embedded memory characterization. 128-133 - Matteo Sonza Reorda, Luca Sterpone, Massimo Violante:
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution. 136-141 - Mohammad Gh. Mohammad, Laila Terkawi:
Fault collapsing for flash memory disturb faults. 142-147 - Philipp Öhler, Sybille Hellebrand:
Low power embedded DRAMs with high quality error correcting capabilities. 148-153 - Fei Xin, Maciej J. Ciesielski, Ian G. Harris:
Design validation of behavioral VHDL descriptions for arbitrary fault models. 156-161 - Franco Fummi, Graziano Pravadelli, Franco Toto:
Coverage of formal properties based on a high-level fault model and functional ATPG. 162-167 - Zhanglei Wang, Krishnendu Chakrabarty:
Built-in self-test of molecular electronics-based nanofabrics. 168-173 - Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer, Chen Wang:
Convolutional compaction-driven diagnosis of scan failures. 176-181 - Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud:
Stuck-open fault diagnosis with stuck-at model. 182-187 - David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre:
Test control for secure scan designs. 190-195 - Adam B. Kinsman, Nicola Nicolici:
Time-multiplexed test data decompression architecture for core-based SOCs with improved utilization of tester channels. 196-201 - Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda:
Exploiting an infrastructure IP to reduce memory diagnosis costs in SoCs. 202-207 - Chuck Hawkins, Jaume Segura:
The anatomy of nanometer timing failures. 210-215 - Hans-Joachim Wunderlich:
From embedded test to embedded diagnosis. 216-221 - Peter Maxwell:
Test for low cost CMOS image sensors. 222- - Hans G. Kerkhoff:
Testing of MEMS-based microsystems. 223-228
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