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ORCID18th ASYNC 2012: Kgs. Lyngby, Denmark
- Jens Sparsø, Montek Singh, Pascal Vivet:
18th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2012, Kgs. Lyngby, Denmark, May 7-9, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-1360-5
Performance Analysis & Optimization
- Tsung-Te Liu, Jan M. Rabaey:
Statistical Analysis and Optimization of Asynchronous Digital Circuits. 1-8 - Mehrdad Najibi, Peter A. Beerel:
Performance Bounds of Asynchronous Circuits with Mode-Based Conditional Behavior. 9-16 - Andrey Mokhov, Danil Sokolov, Alex Yakovlev
:
Adapting Asynchronous Circuits to Operating Conditions by Logic Parametrisation. 17-24
Processor Case Studies
- Nabil Imam, Filipp Akopyan, John V. Arthur, Paul Merolla, Rajit Manohar, Dharmendra S. Modha:
A Digital Neurosynaptic Core Using Event-Driven QDI Circuits. 25-32 - Benjamin Z. Tang, Stephen Longfield Jr., Sunil A. Bhave, Rajit Manohar:
A Low Power Asynchronous GPS Baseband Processor. 33-40
Asynchronous Memories
- Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu:
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism. 41-48 - Jim D. Garside, Stephen B. Furber, Steve Temple, David M. Clark, Luis A. Plana:
An Asynchronous Fully Digital Delay Locked Loop for DDR SDRAM Data Recovery. 49-56
Synthesis and CAD
- John Hansen, Montek Singh:
A Fast Hierarchical Approach to Resource Sharing in Pipelined Asynchronous Systems. 57-64 - Robert B. Reese, Scott C. Smith, Mitchell A. Thornton:
Uncle - An RTL Approach to Asynchronous Design. 65-72 - Yvain Thonnart, Edith Beigné, Pascal Vivet:
A Pseudo-Synchronous Implementation Flow for WCHB QDI Asynchronous Circuits. 73-80
Arithmetic Circuits
- Jiaoyan Chen, Emanuel M. Popovici, Dilip P. Vasudevan, Michel P. Schellekens:
Ultra Low Power Booth Multiplier Using Asynchronous Logic. 81-88 - Basit Riaz Sheikh, Rajit Manohar:
An Asynchronous Floating-Point Multiplier. 89-96 - Navaneeth Jamadagni, Jo C. Ebergen:
An Asynchronous Divider Implementation. 97-104
Industry Practice
- Marc Renaudin, Alain Fonkoua:
Tiempo Asynchronous Circuits System Verilog Modeling Language. 105-112 - Michel Laurence:
Introduction to Octasic Asynchronous Processor Technology. 113-117
GALS and Signaling
- Manoj Kumar Yadav, Mario R. Casu, Maurizio Zamboni:
DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems. 118-125 - Xin Fan, Milos Krstic, Eckhard Grass:
Performance Analysis of GALS Datalink Based on Pausible Clocking. 126-133 - Marco Cannizzaro, Luciano Lavagno:
PID (Partial Inversion Data): An M-of-N Level-Encoded Transition Signaling Protocol for Asynchronous Global Communication. 134-141
Fault Tolerance
- Julian J. H. Pontes, Ney Calazans, Pascal Vivet:
Adding Temporal Redundancy to Delay Insensitive Codes to Mitigate Single Event Effects. 142-149 - Benjamin Stefan Devlin, Makoto Ikeda, Kunihiro Asada:
Self Synchronous Circuits for Error Robust Operation in Sub-100nm Processes. 150-157
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