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2020 – today
- 2024
[c79]Spyridon Spyridonos, Yiorgos Tsiatouhas:
Testing Algorithms for Hard to Detect Thermal Crosstalk Induced Write Disturb Faults in Phase Change Memories. DATE 2024: 1-6- [c78]Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas:
Deep Learning Based Detection of Anti-Reflective Obstacles in VLC Systems. ICAIIC 2024: 401-406 - 2023
- [j24]Helen-Maria Dounavi
, Yiorgos Tsiatouhas:
An aging monitoring scheme for SRAM decoders. Integr. 88: 108-115 (2023) - [c77]Athanasios Xynos, Vasileios Tenentes, Yiorgos Tsiatouhas:
SiCBit-PUF: Strong in-Cache Bitflip PUF Computation for Trusted SoCs. ETS 2023: 1-6 - [c76]Christina Dilopoulou, Yiorgos Tsiatouhas:
BTI Aging Influence in SRAM-based In-Memory Computing Schemes and its Mitigation. ICECS 2023: 1-5 - [c75]Christina Dilopoulou, Yiorgos Tsiatouhas:
BTI Aging Influence and Mitigation in Neural Networks Oriented In-Memory Computing SRAMs. MOCAST 2023: 1-4 - [c74]Vasileios Tenentes, Athanasios Xynos, Christos Zonios, Asimina Koutra, Christina Dilopoulou, Konstantinos Tsampiras, Yiorgos Tsiatouhas, Daniele Rossi:
Embedded Platforms for Trusted Edge Computing Towards Quality Assurance Along the Supply Chain. SEEDA-CECNSM 2023: 1-6 - 2022
- [c73]Christoforos Papaioannou, Marina E. Plissiti, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas:
Signal decoding in an NLOS VLC system with the presence of anti-reflective obstacles. BlackSeaCom 2022: 303-309 - [c72]Spyridon Spyridonos, Yiorgos Tsiatouhas:
BTI Aging Influence on Charge Pump Circuits. MOCAST 2022: 1-4 - [c71]Constantinos Efstathiou, Laura Agalioti, Yiorgos Tsiatouhas:
Efficient Dynamic Logic Magnitude Comparators. VLSI-SoC 2022: 1-5 - 2021
- [j23]Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas:
Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier. J. Electron. Test. 37(1): 65-82 (2021) - [j22]Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos:
A Low-Cost, Robust and Tolerant, Digital Scheme for Post-Bond Testing and Diagnosis of TSVs. J. Electron. Test. 37(2): 191-203 (2021) - [c70]Marina E. Plissiti, Christoforos Papaioannou, Yiorgos Sfikas, Georgios Papatheodorou, Simon-Ilias Poulis, Aristides Efthymiou, Yiorgos Tsiatouhas:
An efficient adaptive thresholding scheme for signal decoding in NLOS VLC systems. MeditCom 2021: 378-382 - 2020
- [c69]Helen-Maria Dounavi, Yiorgos Tsiatouhas:
Monitoring of BTI and HCI Aging in SRAM Decoders. ETS 2020: 1-2 - [c68]Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos:
An Alternative Post-bond Testing Method for TSVs. MOCAST 2020: 1-4
2010 – 2019
- 2019
- [c67]Costas Efstathiou, Yiorgos Tsiatouhas:
On the Static CMOS Implementation of Magnitude Comparators. PATMOS 2019: 103-106 - 2018
- [c66]Costas Efstathiou, K. Dimolikas, Christoforos Papaioannou, Yiorgos Tsiatouhas:
Low Power and High Speed Static CMOS Digital Magnitude Comparators. ICECS 2018: 249-252 - [c65]Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas:
Periodic Aging Monitoring in SRAM Sense Amplifiers. IOLTS 2018: 12-16 - [c64]Helen-Maria Dounavi, Yiorgos Sfikas, Yiorgos Tsiatouhas:
Aging monitoring in SRAM sense amplifiers. MOCAST 2018: 1-4 - 2017
- [c63]Yiorgos Tsiatouhas:
Periodic Bias-Temperature Instability monitoring in SRAM cells. ETS 2017: 1-2 - [c62]Yiorgos Sfikas, Yiorgos Tsiatouhas:
Variation tolerant BTI monitoring in SRAM cells. IOLTS 2017: 100-105 - [c61]Yiorgos Sfikas, Yiorgos Tsiatouhas:
BTI and HCI degradation detection in SRAM cells. MOCAST 2017: 1-4 - [c60]Stylianos-Georgios Papadopoulos, Vasileios Gerakis, Yiorgos Tsiatouhas, Alkis A. Hatzopoulos:
Oscillation-based technique for post-bond parallel testing and diagnosis of multiple TSVs. PATMOS 2017: 1-6 - 2016
- [j21]Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni:
Timing Error Tolerance in Small Core Designs for SoC Applications. IEEE Trans. Computers 65(2): 654-663 (2016) - [j20]Yiorgos Sfikas, Yiorgos Tsiatouhas:
Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs. IEEE Trans. Computers 65(7): 2339-2345 (2016) - [c59]Stefanos Valadimas, Angela Arapoyanni, Yiorgos Tsiatouhas:
Timing error mitigation in microprocessor cores. ICECS 2016: 772-775 - [c58]Raghava Katreepalli, Hemanth Chemanchula, Themistoklis Haniotakis, Yiorgos Tsiatouhas:
Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design. ISVLSI 2016: 367-372 - 2015
- [j19]Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
A current monitoring technique for IDDQ testing in digital integrated circuits. Integr. 50: 48-60 (2015) - [c57]John Liaperdos, Haralampos-G. D. Stratigopoulos, Louay Abdallah, Yiorgos Tsiatouhas, Angela Arapoyanni, Xin Li:
Fast deployment of alternate analog test using Bayesian model fusion. DATE 2015: 1030-1035 - [c56]John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas:
A method for the estimation of defect detection probability of analog/RF defect-oriented tests. DATE 2015: 1395-1400 - [c55]Yiorgos Sfikas, Yiorgos Tsiatouhas, Mottaqiallah Taouil, Said Hamdioui:
On resistive open defect detection in DRAMs: The charge accumulation effect. ETS 2015: 1-6 - [c54]Katerina Katsarou, Yiorgos Tsiatouhas:
Soft error immune latch under SEU related double-node charge collection. IOLTS 2015: 46-49 - [c53]Anthi Anastasiou, Yiorgos Tsiatouhas, Angela Arapoyanni:
On the reuse of existing error tolerance circuitry for low power scan testing. ISCAS 2015: 1578-1581 - [c52]Helen-Maria Dounavi, Yiorgos Tsiatouhas, Angela Arapoyanni:
Scan chain based at-speed diagnosis in the presence of scan output compaction schemes. Panhellenic Conference on Informatics 2015: 419-423 - 2014
- [j18]Efi Arvaniti, Yiorgos Tsiatouhas:
Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique. J. Electron. Test. 30(3): 329-341 (2014) - [j17]Stefanos Valadimas, Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Xrysovalantis Kavousianos:
The Time Dilation Technique for Timing Error Tolerance. IEEE Trans. Computers 63(5): 1277-1286 (2014) - [j16]Ran Wang, Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty:
Built-In Self-Test, Diagnosis, and Repair of MultiMode Power Switches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(8): 1231-1244 (2014) - [j15]Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas:
Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches. IEEE Trans. Very Large Scale Integr. Syst. 22(1): 13-26 (2014) - [j14]Yiorgos Sfikas, Yiorgos Tsiatouhas, Said Hamdioui:
Layout-Based Refined NPSF Model for DRAM Characterization and Testing. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1446-1450 (2014) - [c51]Helen-Maria Dounavi, Yiorgos Tsiatouhas:
Stuck-at fault diagnosis in scan chains. DTIS 2014: 1-6 - [c50]Anthi Anastasiou, Yiorgos Tsiatouhas:
Power efficient scan testing by exploiting existing error tolerance circuitry in a design. ETS 2014: 1-2 - [c49]Katerina Katsarou, Yiorgos Tsiatouhas:
Double node charge sharing SEU tolerant latch design. IOLTS 2014: 122-127 - 2013
- [j13]Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Petros Xarchakos:
Effective Timing Error Tolerance in Flip-Flop Based Core Designs. J. Electron. Test. 29(6): 795-804 (2013) - [j12]John Liaperdos, Angela Arapoyanni, Y. Tsiatouhas:
Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(9): 1383-1394 (2013) - [j11]Costas Efstathiou, Zaher Owda, Yiorgos Tsiatouhas:
New High-Speed Multioutput Carry Look-Ahead Adders. IEEE Trans. Circuits Syst. II Express Briefs 60-II(10): 667-671 (2013) - [j10]John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas:
A Built-In Voltage Measurement Technique for the Calibration of RF Mixers. IEEE Trans. Instrum. Meas. 62(4): 732-742 (2013) - [c48]Katerina Katsarou, Yiorgos Tsiatouhas, Angela Arapoyanni:
NBTI aging tolerance in pipeline based designs NBTI. IOLTS 2013: 31-36 - 2012
- [c47]Efi Arvaniti, Yiorgos Tsiatouhas:
Low power scan by partitioning and scan hold. DDECS 2012: 262-265 - [c46]Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni, Adrian Evans:
Single event upset tolerance in flip-flop based microprocessor cores. DFT 2012: 79-84 - [c45]Ioannis Voyiatzis, Costas Efstathiou, Yiorgos Tsiatouhas, Cleo Sgouropoulou:
A novel architecture to reduce test time in march-based SRAM tests. DTIS 2012: 1-6 - [c44]Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni:
Cost and power efficient timing error tolerance in flip-flop based microprocessor cores. ETS 2012: 1-6 - [c43]Maria Chalkia, Yiorgos Tsiatouhas:
The leafs scan-chain for test application time and scan power reduction. ICECS 2012: 749-752 - [c42]Lampros Dermentzoglou, John Liaperdos, Angela Arapoyanni, Yiorgos Tsiatouhas:
Testing wireless transceivers' RF front-ends utilizing defect-oriented BIST techniques. ICECS 2012: 961-964 - 2011
- [c41]Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty:
Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches. ETS 2011: 13-18 - [c40]Zhaobo Zhang, Xrysovalantis Kavousianos, Yiorgos Tsiatouhas, Krishnendu Chakrabarty:
A BIST scheme for testing and repair of multi-mode power switches. IOLTS 2011: 115-120 - [c39]Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas:
A Robust and Reconfigurable Multi-mode Power Gating Architecture. VLSI Design 2011: 280-285 - 2010
- [j9]Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas:
A Built-In-Test Circuit for RF Differential Low Noise Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(7): 1549-1558 (2010) - [c38]Lambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas:
A Build-In Self-Test technique for RF Mixers. DDECS 2010: 88-92 - [c37]Stefanos Valadimas, Yiorgos Tsiatouhas, Angela Arapoyanni:
Timing error tolerance in nanometer ICs. IOLTS 2010: 283-288 - [c36]Themistoklis Haniotakis, Zaher Owda, Yiorgos Tsiatouhas:
Memory-Less Pipeline Dynamic Circuit Design Technique. ISVLSI 2010: 201-205 - [c35]Yiannis Moisiadis, Yiorgos Tsiatouhas:
A Receiver Circuit for Low-Swing Interconnect Schemes. ISVLSI 2010: 238-241
2000 – 2009
- 2009
- [c34]Yiorgos Sfikas, Yiorgos Tsiatouhas:
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing. DDECS 2009: 108-113 - 2008
- [j8]Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni:
A Current Mode, Parallel, Two-Rail Code Checker. IEEE Trans. Computers 57(8): 1032-1045 (2008) - [c33]Andreas Floros, Yiorgos Tsiatouhas, Xrysovalantis Kavousianos:
Timing Error Detection and Correction by Time Dilation. VLSI-SoC (Selected Papers) 2008: 271-285 - 2007
- [j7]Yiorgos Tsiatouhas:
A Stress-Relaxed Negative Voltage-Level Converter. IEEE Trans. Circuits Syst. II Express Briefs 54-II(3): 282-286 (2007) - [j6]Themistoklis Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou:
Testable Designs of Multiple Precharged Domino Circuits. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 461-465 (2007) - [c32]Yiorgos Tsiatouhas, Angela Arapoyanni, Dionisis Skias:
A Scan Flip-Flop for Low-Power Scan Operation. ICECS 2007: 439-442 - [c31]Lampros Dermentzoglou, Anastasios Karagounis, Aggeliki Arapoyanni, Yiorgos Tsiatouhas:
An Embedded Test Circuit for RF Single Ended Low Noise Amplifiers. ICECS 2007: 1119-1122 - 2006
- [j5]Konstantinos Limniotis, Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni:
A Design Technique for Energy Reduction in NORA CMOS Logic. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(12): 2647-2655 (2006) - [c30]Andreas Floros, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism. ICECS 2006: 692-695 - [c29]Y. Tsiatouhas, Angela Arapoyanni:
High fan-in differential current mirror logic. ISCAS 2006 - 2005
- [c28]Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, Guillaume Prenat, Salvador Mir:
A built-in IDDQ testing circuit. ESSCIRC 2005: 471-474 - [c27]Sotirios Matakias, Yiorgos Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
An embedded IDDQ testing circuit and technique. ICECS 2005: 1-4 - [c26]Sotirios Matakias, Y. Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, Aristides Efthymiou:
Fast, Parallel Two-Rail Code Checker with Enhanced Testability. IOLTS 2005: 149-156 - [c25]Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni:
A Built-In Self-Test Scheme for Differential Ring Oscillators. ISQED 2005: 448-452 - [c24]A. Rao, Th. Haniotakis, Y. Tsiatouhas, H. Djemil:
The Use of Pre-Evaluation Phase in Dynamic CMOS Logic. ISVLSI 2005: 270-271 - 2004
- [j4]Lampros Dermentzoglou, Y. Tsiatouhas, Angela Arapoyanni:
A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators. J. Electron. Test. 20(2): 133-142 (2004) - [j3]Sotirios Matakias, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs. J. Electron. Test. 20(5): 523-531 (2004) - [c23]A. Rao, Th. Haniotakis, Y. Tsiatouhas, V. Kaky:
A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations. IOLTS 2004: 52-57 - [c22]Sotirios Matakias, Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni:
Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications . ISVLSI 2004: 293-296 - 2003
- [c21]Yiorgos Tsiatouhas, Konstantinos Limniotis, Angela Arapoyanni, Themistoklis Haniotakis:
A low power NORA circuit design technique based on charge recycling. ICECS 2003: 224-227 - [c20]Lampros Dermentzoglou, Yiorgos Tsiatouhas, Angela Arapoyanni:
A novel scheme for testing radio frequency voltage controlled oscillators. ICECS 2003: 595-598 - [c19]Y. Tsiatouhas, Sotirios Matakias, Angela Arapoyanni, Th. Haniotakis:
A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs. IOLTS 2003: 12-16 - [c18]Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni:
An Embedded IDDQ Testing Architecture and Technique. ISQED 2003: 442-445 - 2002
- [j2]Y. Tsiatouhas, Yiannis Moisiadis, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni:
A new technique for IDDQ testing in nanometer technologies. Integr. 31(2): 183-194 (2002) - [c17]Y. Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, Th. Haniotakis:
A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing. IOLTW 2002: 56-60 - [c16]A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni, Themistoklis Haniotakis:
SRAM oriented memory sense amplifier design in 0.18 μm CMOS technology. ISCAS (5) 2002: 145-148 - [c15]Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Angela Arapoyanni:
Extending the Viability of IDDQ Testing in the Deep Submicron Era. ISQED 2002: 100-105 - 2001
- [c14]A. Chrisanthopoulos, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni:
New test pattern generation units for NPSF oriented memory built-in self test. ICECS 2001: 749-752 - [c13]A. Chrisanthopoulos, Yiannis Moisiadis, A. Varagis, Y. Tsiatouhas, Angela Arapoyanni:
A new flash memory sense amplifier in 0.18 μm CMOS technology. ICECS 2001: 941-944 - [c12]Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos, Costas Efstathiou:
Concurrent Detection of Soft Errors Based on Current Monitoring. IOLTW 2001: 106-110 - 2000
- [j1]George Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas, Angela Arapoyanni:
Management of charge pump circuits. Integr. 30(1): 91-101 (2000) - [c11]Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos:
A Versatile Built-In Self-Test Scheme for Delay Fault Testing. DATE 2000: 756 - [c10]Y. Tsiatouhas, A. Chrisanthopoulos, George Kamoulakos, Th. Haniotakis:
New memory sense amplifier designs in CMOS technology. ICECS 2000: 19-22 - [c9]A. Chrisanthopoulos, George Kamoulakos, Y. Tsiatouhas, Angela Arapoyanni:
A test pattern generation unit for memory NPSF built-in self test. ICECS 2000: 425-428 - [c8]Dionisis Skias, Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni:
A state assignment algorithm for finite state machines. ICECS 2000: 823-826 - [c7]Y. Tsiatouhas, Th. Haniotakis, Dimitris Nikolos:
A Compact Built-In Current Sensor for IDDQ Testing. IOLTW 2000: 95-99 - [c6]Th. Haniotakis, Y. Tsiatouhas, Dimitris Nikolos, Costas Efstathiou:
On Testability of Multiple Precharged Domino Logic. ISQED 2000: 299-304
1990 – 1999
- 1999
- [c5]Dimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas:
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks. DATE 1999: 112-116 - [c4]Y. Tsiatouhas, Th. Haniotakis:
A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. DFT 1999: 95-100 - [c3]Haridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis:
On Path Delay Fault Testing of Multiplexer - Based Shifters. Great Lakes Symposium on VLSI 1999: 20-23 - [c2]Th. Haniotakis, Y. Tsiatouhas, Angela Arapoyanni:
Novel domino logic designs. ICECS 1999: 213-216 - 1998
- [c1]Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas:
C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. DFT 1998: 155-163
Coauthor Index
Angela Arapoyanni
aka: Aggeliki Arapoyanni
aka: Aggeliki Arapoyanni
Themistoklis Haniotakis
aka: Th. Haniotakis
aka: Th. Haniotakis
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