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ORCIDRajeev Barua
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- affiliation: University of Maryland, College Park, USA
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2020 – today
- 2021
[c42]Amir Majlesi-Kupaei, Danny Kim, Rajeev Barua:
RL-BIN++: Overcoming Binary Instrumentation Challenges in the Presence of Obfuscation Techniques and Problematic Features. ICSCA 2021: 262-272
2010 – 2019
- 2018
- [j20]Fady Ghanim
, Uzi Vishkin, Rajeev Barua:
Easy PRAM-Based High-Performance Parallel Programming with ICE. IEEE Trans. Parallel Distributed Syst. 29(2): 377-390 (2018) - [c41]Danny Kim, Daniel Mirsky, Amir Majlesi-Kupaei, Rajeev Barua:
A Hybrid Static Tool to Increase the Usability and Scalability of Dynamic Detection of Malware. MALWARE 2018: 115-123 - 2017
- [c40]Amir Majlesi-Kupaei, Danny Kim, Kapil Anand, Khaled ElWazeer, Rajeev Barua:
RL-Bin, Robust Low-overhead Binary Rewriter. FEAST@CCS 2017: 17-22 - [c39]Danny Kim, Amir Majlesi-Kupaei, Julien Roy, Kapil Anand, Khaled ElWazeer, Daniel Buettner, Rajeev Barua:
DynODet: Detecting Dynamic Obfuscation in Malware. DIMVA 2017: 97-118 - 2016
- [j19]Timothy Creech, Rajeev Barua:
Transparently Space Sharing a Multicore Among Multiple Processes. ACM Trans. Parallel Comput. 3(3): 17:1-17:35 (2016) - [j18]Kapil Anand, Khaled Elwazeer, Aparna Kotha, Matthew Smithson, Rajeev Barua, Angelos D. Keromytis:
A Stack Memory Abstraction and Symbolic Analysis Framework for Executables. ACM Trans. Softw. Eng. Methodol. 25(2): 19:1-19:38 (2016) - [c38]Fady Ghanim, Rajeev Barua, Uzi Vishkin:
POSTER: Easy PRAM-based High-Performance Parallel Programming with ICE. PACT 2016: 419-420 - 2015
- [j17]Kapil Anand, Rajeev Barua:
Instruction-Cache Locking for Improving Embedded Systems Performance. ACM Trans. Embed. Comput. Syst. 14(3): 53:1-53:25 (2015) - [j16]Aparna Kotha, Kapil Anand, Timothy Creech, Khaled Elwazeer, Matthew Smithson, Greeshma Yellareddy, Rajeev Barua:
Affine Parallelization Using Dependence and Cache Analysis in a Binary Rewriter. IEEE Trans. Parallel Distributed Syst. 26(8): 2154-2163 (2015) - 2014
- [j15]Alexandros Tzannes, George C. Caragea, Uzi Vishkin, Rajeev Barua:
Lazy Scheduling: A Runtime Adaptive Scheduler for Declarative Parallelism. ACM Trans. Program. Lang. Syst. 36(3): 10:1-10:51 (2014) - [c37]Kyungjin Yoo, Rajeev Barua:
Recovery of Object Oriented Features from C++ Binaries. APSEC (1) 2014: 231-238 - [c36]Aparna Kotha, Kapil Anand, Timothy Creech, Khaled Elwazeer, Matthew Smithson, Rajeev Barua:
Affine Parallelization of Loops with Run-Time Dependent Bounds from Binaries. ESOP 2014: 554-574 - [c35]Aroon Sharma, Darren Smith, Joshua Koehler, Rajeev Barua, Michael Ferguson:
Affine Loop Optimization Based on Modulo Unrolling in Chapel. PGAS 2014: 13:1-13:12 - 2013
- [j14]Matthew S. Simpson, Rajeev Barua:
MemSafe: ensuring the spatial and temporal memory safety of C at runtime. Softw. Pract. Exp. 43(1): 93-128 (2013) - [j13]Leila Ismail, Rajeev Barua:
Implementation and performance evaluation of a distributed conjugate gradient method in a cloud computing environment. Softw. Pract. Exp. 43(3): 281-304 (2013) - [c34]Kapil Anand, Matthew Smithson, Khaled Elwazeer, Aparna Kotha, Jim Gruen, Nathan Giles, Rajeev Barua:
A compiler-level intermediate representation based binary analysis and rewriting system. EuroSys 2013: 295-308 - [c33]Kapil Anand, Khaled Elwazeer, Aparna Kotha, Matthew Smithson, Rajeev Barua, Angelos D. Keromytis:
An Accurate Stack Memory Abstraction and Symbolic Analysis Framework for Executables. ICSM 2013: 90-99 - [c32]Timothy Creech, Aparna Kotha, Rajeev Barua:
Efficient multiprogramming for multicores with SCAF. MICRO 2013: 334-345 - [c31]Khaled Elwazeer, Kapil Anand, Aparna Kotha, Matthew Smithson, Rajeev Barua:
Scalable variable and data type detection in a binary rewriter. PLDI 2013: 51-60 - [c30]Matthew Smithson, Khaled Elwazeer, Kapil Anand, Aparna Kotha, Rajeev Barua:
Static binary rewriting without supplemental information: Overcoming the tradeoff between coverage and correctness. WCRE 2013: 52-61 - 2011
- [j12]George C. Caragea, Alexandros Tzannes, Fuat Keceli, Rajeev Barua, Uzi Vishkin:
Resource-Aware Compiler Prefetching for Fine-Grained Many-Cores. Int. J. Parallel Program. 39(5): 615-638 (2011) - [c29]Alexandros Tzannes, Rajeev Barua, Uzi Vishkin:
Improving Run-Time Scheduling for General-Purpose Parallel Code. PACT 2011: 216 - [c28]Fuat Keceli, Alexandros Tzannes, George C. Caragea, Rajeev Barua, Uzi Vishkin:
Toolchain for Programming, Simulating and Studying the XMT Many-Core Architecture. IPDPS Workshops 2011: 1282-1291 - [c27]Pádraig O'Sullivan, Kapil Anand, Aparna Kotha, Matthew Smithson, Rajeev Barua, Angelos D. Keromytis:
Retrofitting Security in COTS Software with Binary Rewriting. SEC 2011: 154-172 - 2010
- [c26]George C. Caragea, Alexandros Tzannes, Fuat Keceli, Rajeev Barua, Uzi Vishkin:
Resource-Aware Compiler Prefetching for Many-Cores. ISPDC 2010: 133-140 - [c25]Aparna Kotha, Kapil Anand, Matthew Smithson, Greeshma Yellareddy, Rajeev Barua:
Automatic Parallelization in a Binary Rewriter. MICRO 2010: 547-557 - [c24]Alexandros Tzannes, George C. Caragea, Rajeev Barua, Uzi Vishkin:
Lazy binary-splitting: a run-time adaptive work-stealing scheduler. PPoPP 2010: 179-190 - [c23]Matthew S. Simpson, Rajeev Barua:
MemSafe: Ensuring the Spatial and Temporal Memory Safety of C at Runtime. SCAM 2010: 199-208 - [e1]Vinod Kathail, Reid Tatge, Rajeev Barua:
Proceedings of the 2010 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2010, Scottsdale, AZ, USA, October 24-29, 2010. ACM 2010, ISBN 978-1-60558-903-9 [contents]
2000 – 2009
- 2009
- [j11]Nghi Nguyen, Angel Dominguez, Rajeev Barua:
Memory allocation for embedded systems with a compile-time-unknown scratch-pad size. ACM Trans. Embed. Comput. Syst. 8(3): 21:1-21:32 (2009) - [c22]Kapil Anand, Rajeev Barua:
Instruction cache locking inside a binary rewriter. CASES 2009: 185-194 - 2008
- [j10]Bhuvan Middha, Matthew S. Simpson, Rajeev Barua:
MTSS: Multitask stack sharing for embedded systems. ACM Trans. Embed. Comput. Syst. 7(4): 46:1-46:37 (2008) - 2007
- [c21]Angel Dominguez, Nghi Nguyen, Rajeev Barua:
Recursive function data allocation to scratch-pad memory. CASES 2007: 65-74 - [c20]Nghi Nguyen, Angel Dominguez, Rajeev Barua:
Scratch-pad memory allocation without compiler support for java applications. CASES 2007: 85-94 - 2006
- [j9]Sumesh Udayakumaran, Angel Dominguez, Rajeev Barua:
Dynamic allocation for scratch-pad memory using compile-time decisions. ACM Trans. Embed. Comput. Syst. 5(2): 472-511 (2006) - [j8]Surupa Biswas, Thomas W. Carley, Matthew S. Simpson, Bhuvan Middha, Rajeev Barua:
Memory overflow protection for embedded systems using run-time checks, reuse, and compression. ACM Trans. Embed. Comput. Syst. 5(4): 719-752 (2006) - [c19]Sumesh Udayakumaran, Rajeev Barua:
An integrated scratch-pad allocator for affine and non-affine code. DATE 2006: 925-930 - 2005
- [j7]Steve Haga, Andrew Webber, Yi Zhang, Nghi Nguyen, Rajeev Barua:
Reducing code size in VLIW instruction scheduling. J. Embed. Comput. 1(3): 415-433 (2005) - [j6]Angel Dominguez, Sumesh Udayakumaran, Rajeev Barua:
Heap data allocation to scratch-pad memory in embedded systems. J. Embed. Comput. 1(4): 521-540 (2005) - [j5]Steve Haga, Natasha Reeves, Rajeev Barua, Diana Marculescu:
Dynamic Functional Unit Assignment for Low Power. J. Supercomput. 31(1): 47-62 (2005) - [c18]Matthew S. Simpson, Bhuvan Middha, Rajeev Barua:
Segment protection for embedded systems using run-time checks. CASES 2005: 66-77 - [c17]Nghi Nguyen, Angel Dominguez, Rajeev Barua:
Memory allocation for embedded systems with a compile-time-unknown scratch-pad size. CASES 2005: 115-125 - [c16]Bhuvan Middha, Matthew S. Simpson, Rajeev Barua:
MTSS: multi task stack sharing for embedded systems. CASES 2005: 191-201 - 2004
- [j4]Yi Zhang, Steve Haga, Rajeev Barua:
Execution History Guided Instruction Prefetching. J. Supercomput. 27(2): 129-147 (2004) - [c15]Surupa Biswas, Matthew S. Simpson, Rajeev Barua:
Memory overflow protection for embedded systems using run-time checks, reuse and compression. CASES 2004: 280-291 - 2003
- [c14]Sumesh Udayakumaran, Rajeev Barua:
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems. CASES 2003: 276-286 - [c13]Steve Haga, Natasha Reeves, Rajeev Barua, Diana Marculescu:
Dynamic Functional Unit Assignment for Low Power. DATE 2003: 11052-11057 - [c12]Thomas W. Carley, Moussa A. Ba, Rajeev Barua, David B. Stewart:
Contention-Free Periodic Message Scheduler Medium Access Control in Wireless Sensor / Actuator Networks. RTSS 2003: 298-307 - [p1]Steve Haga, Natasha Reeves, Rajeev Barua, Diana Marculescu:
Dynamic Functional Unit Assignment for Low Power. Embedded Software for SoC 2003: 485-497 - 2002
- [j3]Oren Avissar, Rajeev Barua, Dave Stewart:
An optimal memory allocation scheme for scratch-pad-based embedded systems. ACM Trans. Embed. Comput. Syst. 1(1): 6-26 (2002) - [c11]T. Vinod Kumar Gupta, Roberto E. Ko, Rajeev Barua:
Compiler-directed customization of ASIP cores. CODES 2002: 97-102 - [c10]Yi Zhang, Steve Haga, Rajeev Barua:
Execution history guided instruction prefetching. ICS 2002: 199-208 - 2001
- [j2]Rajeev Barua, Walter Lee, Saman P. Amarasinghe, Anant Agarwal:
Compiler Support for Scalable and Efficient Memory Systems. IEEE Trans. Computers 50(11): 1234-1247 (2001) - [c9]Oren Avissar, Rajeev Barua, Dave Stewart:
Heterogeneous memory management for embedded systems. CASES 2001: 34-43 - [c8]Anant Agarwal, David A. Kranz, Rajeev Barua, Venkat Natarajan:
Optimal Tiling for Minimizing Communication in Distributed Shared-Memory Multiprocessors. Compiler Optimizations for Scalable Parallel Systems Languages 2001: 285-338 - 2000
- [b1]Rajeev Barua:
Compiler-managed memory system for software-exposed architectures. Massachusetts Institute of Technology, Cambridge, MA, USA, 2000
1990 – 1999
- 1999
- [c7]Jonathan Babb, Martin C. Rinard, Csaba Andras Moritz, Walter Lee, Matthew I. Frank, Rajeev Barua, Saman P. Amarasinghe:
Parallelizing Applications into Silicon. FCCM 1999: 70- - [c6]Rajeev Barua, Walter Lee, Saman P. Amarasinghe, Anant Agarwal:
Maps: A Compiler-Managed Memory System for Raw Machines. ISCA 1999: 4-15 - 1998
- [c5]Walter Lee, Rajeev Barua, Matthew I. Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman P. Amarasinghe:
Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine. ASPLOS 1998: 46-57 - [c4]Rajeev Barua, Walter Lee, Saman P. Amarasinghe, Anant Agarwal:
Memory bank disambiguation using modulo unrolling for Raw machines. HiPC 1998: 212-220 - [c3]Frederic T. Chong, Rajeev Barua, Fredrik Dahlgren, John Kubiatowicz, Anant Agarwal:
The Sensitivity of Communication Mechanisms to Bandwidth and Latency. HPCA 1998: 37-46 - 1997
- [j1]Elliot Waingold, Michael B. Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew I. Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman P. Amarasinghe, Anant Agarwal:
Baring It All to Software: Raw Machines. Computer 30(9): 86-93 (1997) - [c2]Jonathan Babb, Matthew I. Frank, Victor Lee, Elliot Waingold, Rajeev Barua, Michael B. Taylor, Jang Kim, Devabhaktuni Srikrishna, Anant Agarwal:
The RAW benchmark suite: computation structures for general purpose computing. FCCM 1997: 134-144 - 1996
- [c1]Rajeev Barua, David A. Kranz, Anant Agarwal:
Communication-Minimal Partitioning of Parallel Loops and Data Arrays for Cache-Coherent Distributed-Memory Multiprocessors. LCPC 1996: 350-368
Coauthor Index
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