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2020 – today
- 2020
[c32]Yu-Chin Hsu, Robert Chen-Hao Chang
:
Intelligent Chips and Technologies for AIoT Era. A-SSCC 2020: 1-4
2010 – 2019
- 2018
- [j23]Ming-Yuan Hsieh, Yu-Chin Hsu, Ching-Torng Lin:
Risk assessment in new software development projects at the front end: a fuzzy logic approach. J. Ambient Intell. Humaniz. Comput. 9(2): 295-305 (2018) - 2016
- [c31]Chia-Chien Hsu, Yu-Chin Hsu, Ching-Torng Lin:
Towards Understanding Senior Citizens' Gateball Participations Behavior and Well-Being: An Application of the Theory of Planned Behavior. HCI (5) 2016: 466-477 - 2012
- [c30]Yu-Chin Hsu, Rong-Huei Chen, Chih-Ming Fan:
Identifying ill tool combinations via Gibbs sampler for semiconductor manufacturing yield diagnosis. WSC 2012: 199:1-199:12 - 2011
- [c29]Gary Miller, Bandana Bhattarai, Yu-Chin Hsu, Jay Dutt, Xi Chen, George Bakewell:
A method to leverage pre-silicon collateral and analysis for post-silicon testing and validation. DAC 2011: 575-578
2000 – 2009
- 2008
- [c28]Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu:
A General Failure Candidate Ranking Framework for Silicon Debug. VTS 2008: 352-358 - 2007
- [c27]Eric Cheung, Xi Chen, Fur-Shing Tsai, Yu-Chin Hsu, Harry Hsieh:
Bridging RTL and gate: correlating different levels of abstraction for design debugging. HLDVT 2007: 73-80 - 2006
- [c26]Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang:
Visibility enhancement for silicon debug. DAC 2006: 13-18 - [c25]Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Ta-Yung Liu, Yu-Chin Hsu:
Diagnosing Silicon Failures Based on Functional Test Patterns. MTV 2006: 94-98 - 2003
- [c24]Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai:
Advanced techniques for RTL debugging. DAC 2003: 362-367 - 2002
- [j22]Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai:
Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. ACM Trans. Design Autom. Electr. Syst. 7(1): 217-230 (2002) - 2000
- [j21]Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai:
Timing optimization on routed designs with incremental placementand routing characterization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 188-196 (2000)
1990 – 1999
- 1999
- [c23]Enoch Hwang, Frank Vahid, Yu-Chin Hsu:
FSMD Functional Partitioning for Low Power. DATE 1999: 22-27 - [c22]Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai:
Post-routing timing optimization with routing characterization. ISPD 1999: 30-35 - 1998
- [j20]Frank Vahid, Thuy Dm Le, Yu-Chin Hsu:
Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance. ACM Trans. Design Autom. Electr. Syst. 3(2): 181-208 (1998) - [j19]Alan Su, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee:
Eliminating false loops caused by sharing in control path. ACM Trans. Design Autom. Electr. Syst. 3(3): 487-495 (1998) - 1997
- [j18]Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita:
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping. Des. Autom. Embed. Syst. 2(3-4): 319-338 (1997) - [j17]Fur-Shing Tsai, Yu-Chin Hsu:
Layout Modeling and Design Space Exploration in Pss1 System. VLSI Design 5(2): 211-221 (1997) - [c21]Cheng-Tsung Hwang, Hsiao-Chien Weng, Yu-Chin Hsu, Mike Tien-Chien Lee:
On the control-subroutine implementation of subprogram synthesis. ASP-DAC 1997: 587-592 - 1996
- [j16]How-Rern Lin, Yu-Chin Hsu, TingTing Hwang:
Cell height driven transistor sizing in a cell based static CMOS module design. IEEE J. Solid State Circuits 31(5): 668-676 (1996) - [c20]Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita:
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL. DAC 1996: 585-590 - [c19]Alan Su, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee:
Eliminating False Loops Caused by Sharing in Control Path. ISSS 1996: 39-44 - [c18]Frank Vahid, Thuy Dm Le, Yu-Chin Hsu:
A Comparison of Functional and Structural Partitioning. ISSS 1996: 121-126 - 1995
- [j15]Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang:
A new approach to schedule operations across nested-ifs and nested-loops. Microprocess. Microprogramming 41(1): 37-52 (1995) - [j14]Shih-Hsu Huang, Yu-Chin Hsu, Yen-Jen Oyang:
A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits. Microprocess. Microprogramming 41(7): 501-519 (1995) - [c17]Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang:
Synthesis of false loop free circuits. ASP-DAC 1995 - 1994
- [j13]Ting-Hai Chao, Yu-Chin Hsu:
Rectilinear Steiner tree construction by local and global refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 303-309 (1994) - [j12]Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King:
MULTIPAR: behavioral partition for synthesizing multiprocessor architectures. IEEE Trans. Very Large Scale Integr. Syst. 2(1): 21-32 (1994) - [c16]How-Rern Lin, Ching-Lung Chou, Yu-Chin Hsu, TingTing Hwang:
Cell Height Driven Transistor Sizing in a Cell Based Module Design. EDAC-ETC-EUROASIC 1994: 425-429 - 1993
- [j11]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(3): 410-424 (1993) - [j10]Cheng-Tsung Hwang, Yu-Chin Hsu:
Zone scheduling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7): 926-934 (1993) - [j9]Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin:
PLS: a scheduler for pipeline synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9): 1279-1286 (1993) - [c15]Yuan-Long Jeang, Yu-Chin Hsu, Jhing-Fa Wang, Jau-Yien Lee:
High throughput pipelined data path synthesis by conserving the regularity of nested loops. ICCAD 1993: 450-453 - 1992
- [j8]Fur-Shing Tsai, Yu-Chin Hsu:
STAR: An automatic data path allocator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(9): 1053-1064 (1992) - [c14]Ting-Hai Chao, Yu-Chin Hsu, Jan-Ming Ho:
Zero Skew Clock Net Routing. DAC 1992: 518-523 - [c13]Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang:
A new approach to schedule operations across nested-ifs and nested-loops. MICRO 1992: 268-271 - 1991
- [j7]Yu-Chin Hsu, Youn-Long Lin, Hang-Ching Hsieh, Ting-Hai Chao:
Combining Logic Minimization and Folding for PLA's. IEEE Trans. Computers 40(6): 706-713 (1991) - [j6]Cheng-Tsung Hwang, Jiahn-Humg Lee, Yu-Chin Hsu:
A formal approach to the scheduling problem in high level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4): 464-475 (1991) - [j5]Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu:
LiB: a CMOS cell compiler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 994-1005 (1991) - [c12]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. DAC 1991: 481-486 - [c11]Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin:
Scheduling for Functional Pipelining and Loop Winding. DAC 1991: 764-769 - [c10]Shi-Zheng Lin, Cheng-Tsung Hwang, Yu-Chin Hsu:
Efficient Microcode Arrangement and Controller Synthesis for Application Specific Integrated Circuits. ICCAD 1991: 38-41 - 1990
- [j4]Youn-Long Lin, Yu-Chin Hsu:
A new algorithm for tile generation. Integr. 9(3): 259-269 (1990) - [j3]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
Hybrid routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 151-157 (1990) - [j2]Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu:
A fast transistor-chaining algorithm for CMOS cell layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 781-786 (1990) - [c9]Cheng-Tsung Hwang, Yu-Chin Hsu, Youn-Long Lin:
Optimum and Heuristic Data Path Scheduling Under Resource Constraints. DAC 1990: 65-70 - [c8]Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu:
LiB: A Cell Layout Generator. DAC 1990: 474-479 - [c7]Chu-Yi Huang, Yen-Shen Chen, Youn-Long Lin, Yu-Chin Hsu:
Data Path Allocation Based on Bipartite Weighted Matching. DAC 1990: 499-504 - [c6]Fur-Shing Tsai, Yu-Chin Hsu:
Data Path Construction and Refinement. ICCAD 1990: 308-311 - [c5]Ting-Hai Chao, Yu-Chin Hsu:
Rectilinear Steiner Tree Construction by Local and Global Refinement. ICCAD 1990: 432-435
1980 – 1989
- 1989
- [j1]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
SILK: a simulated evolution router. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(10): 1108-1114 (1989) - [c4]Jiahn-Humg Lee, Yu-Chin Hsu, Youn-Long Lin:
A new integer linear programming formulation for the scheduling problem in data path synthesis. ICCAD 1989: 20-23 - [c3]Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu:
An optimal transistor-chaining algorithm for CMOS cell layout. ICCAD 1989: 344-347 - [c2]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
Routing using a pyramid data structure. ICCAD 1989: 436-439 - 1988
- [c1]Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai:
A detailed router based on simulated evolution. ICCAD 1988: 38-41 - 1987
- [b1]Yu-Chin Hsu:
Floor Planning and Global Routing in an Automated Chip Design System. University of Illinois Urbana-Champaign, USA, 1987
Coauthor Index
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