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ORCIDSergei Sawitzki
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2010 – 2019
- 2017
[c23]Thomas Fabian Starke, Timm Bostelmann, Sergei Sawitzki:
FPGA-basierter Protein- und DNA-Sequenzvergleich zur optimierten Datenbanksuche mit dem BLAST-Algorithmus. GI-Jahrestagung 2017: 469-480- 2015
- [c22]Timm Bostelmann, Sergei Sawitzki:
Towards a guided design flow for heterogeneous reconfigurable architectures. FPL 2015: 1-2 - 2014
- [c21]Timm Bostelmann, Sergei Sawitzki:
A conceptual toolchain for an application domain specific reconfigurable logic architecture. ReConFig 2014: 1-4 - 2013
- [c20]Timm Bostelmann, Sergei Sawitzki:
Improving FPGA placement with a self-organizing map. ReConFig 2013: 1-6 - 2012
- [j3]Stefan Schulze, Sergej Sawitzki:
Processor design using a functional hardware description language. Microprocess. Microsystems 36(8): 676-694 (2012) - 2011
- [c19]Stefan Schulze, Sergei Sawitzki:
Design, Implementation, and Verification of an Adaptable Processor in Lava HDL. ARC 2011: 145-156 - 2010
- [j2]Irfan Habib, Özgün Paker, Sergei Sawitzki:
Design Space Exploration of Hard-Decision Viterbi Decoding: Algorithm and VLSI Implementation. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 794-807 (2010)
2000 – 2009
- 2008
- [j1]John Dielissen, Nur Engin, Sergei Sawitzki, Kees van Berkel:
Multistandard FEC Decoders for Wireless Devices. IEEE Trans. Circuits Syst. II Express Briefs 55-II(3): 284-288 (2008) - [c18]Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki:
A Novel Routing Architecture for Field-Programmable Gate-Arrays. ARCS 2008: 144-158 - [c17]Alexander Danilin, Sergei Sawitzki, Erik Rijshouwer:
Reconfigurable cell architecture for multi-standard interleaving and deinterleaving in digital communication systems. FPL 2008: 527-530 - 2007
- [c16]Gummidipudi Krishnaiah, Nur Engin, Sergei Sawitzki:
Scalable reconfigurable channel decoder architecture for future wireless handsets. DATE 2007: 1563-1568 - [c15]Micha Nelissen, Kees van Berkel, Sergei Sawitzki:
Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance. FPL 2007: 521-524 - 2006
- [c14]Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki:
Astra: An Advanced Space-Time Reconfigurable Architecture. FPL 2006: 1-4 - 2005
- [c13]Alexander Danilin, Martijn T. Bennebroek, Sergei Sawitzki:
A Novel Toolset for the Development of FPGA-like Reconfigurable Logic. FPL 2005: 640-643 - 2004
- [c12]Alexander Danilin, Sergei Sawitzki:
Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs. FPL 2004: 852-856 - 2003
- [c11]Sergej Sawitzki, Rainer G. Spallek:
Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms. FPL 2003: 1119-1122 - 2002
- [b1]Sergei Sawitzki:
Anwendungsparallelität und rekonfigurierbare Rechnersysteme - Entwurfsraum, Architekturvorlage, Entwurfsfluß. Dresden University of Technology, Germany, Mensch und Buch 2002, ISBN 978-3-89820-407-1, pp. I-XX, 1-12 - [c10]Steffen Köhler, Jens Braunes, Sergej Sawitzki, Rainer G. Spallek:
Improving Code Efficiency for Reconfigurable VLIW Processors. IPDPS 2002 - [p1]Sergei Sawitzki:
Architektur und Entwurfsfluss zur Unterstützung der Anwendungsparallelität durch rekonfigurierbare Rechnersysteme. Ausgezeichnete Informatikdissertationen 2002: 143-152 - 2001
- [c9]John Dielissen, Jef L. van Meerbergen, Marco Bekooij, Françoise Harmsze, Sergej Sawitzki, Jos Huisken
, Albert van der Werf:
Power-efficient layered turbo decoder processor. DATE 2001: 246-251 - [c8]Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek:
Prototyping Framework for Reconfigurable Processors. FPL 2001: 6-16 - 2000
- [c7]Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube:
Formal Verification for Microprocessors with Extendable Instruction Set. ASAP 2000: 47-55 - [c6]Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube:
Formal Verification of a Reconfigurable Microprocessor. FPL 2000: 781-784 - [c5]Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek, Jörg Schneider, S. Rülke:
Experimenteller Vergleich verschiedener Entwurfsmethoden für FPGA-basierte Entwurfsabläufe. MBMV 2000: 236-244
1990 – 1999
- 1999
- [c4]Sergej Sawitzki, Rainer G. Spallek:
A Concept for an Evaluation Framework for Reconfigurable Systems. FPL 1999: 475-480 - [c3]Sergej Sawitzki:
Gestaltung und Simulation hardware-rekonfigurierbarer Rechnersysteme. GI Jahrestagung 1999: 239-246 - [c2]Steffen Köhler, Sergej Sawitzki, Achim Gratz, Rainer G. Spallek:
Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic. IPPS/SPDP Workshops 1999: 706-708 - 1998
- [c1]Sergej Sawitzki, Achim Gratz, Rainer G. Spallek:
Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays. FPL 1998: 411-415
Coauthor Index
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