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ORCIDJavier Mora 0001
Person information
- affiliation: Universidad Politécnica de Madrid, Spain
Other persons with the same name
- Javier Mora 0002 — University of Ottawa, Ontario, Canada
- Javier Mora 0003 — University of Chile, School of Medicine, Surgery Department, Santiago, Chile
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2010 – 2019
- 2019
[j3]Javier Mora
, Rubén Salvador, Eduardo de la Torre:
On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming. Genet. Program. Evolvable Mach. 20(2): 155-186 (2019)- [c12]Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre:
Automated Tool and Runtime Support for Fine-Grain Reconfiguration in Highly Flexible Reconfigurable Systems. FCCM 2019: 307 - 2018
- [j2]Javier Mora, Eduardo de la Torre:
Accelerating the evolution of a systolic array-based evolvable hardware system. Microprocess. Microsystems 56: 144-156 (2018) - [c11]Rafael Zamacola, Alberto García-Martínez, Javier Mora, Andrés Otero, Eduardo de la Torre:
IMPRESS: Automated Tool for the Implementation of Highly Flexible Partial Reconfigurable Systems with Xilinx Vivado. ReConFig 2018: 1-8 - 2015
- [c10]Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. ReCoSoC 2015: 1-7 - 2013
- [j1]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. IEEE Trans. Computers 62(8): 1481-1493 (2013) - [c9]Javier Mora, Angel Gallego, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. DASIP 2013: 182-189 - [c8]Javier Mora, Angel Gallego, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo:
A noise-agnostic self-adaptive image processing application based on evolvable hardware. DASIP 2013: 351-352 - [c7]Angel Gallego, Javier Mora, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo:
A self-adaptive image processing application based on evolvable and scalable hardware. FPL 2013: 1 - [c6]Angel Gallego, Javier Mora, Andrés Otero, Rubén Salvador, Eduardo de la Torre, Teresa Riesgo:
A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays. IPDPS Workshops 2013: 182-191 - [c5]Angel Gallego, Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
A scalable evolvable hardware processing array. ReConFig 2013: 1-7 - 2012
- [c4]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. FPL 2012: 547-550 - 2011
- [c3]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. AHS 2011: 184-191 - [c2]Andrés Otero, Rubén Salvador, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. AHS 2011: 336-343 - [c1]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo:
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. ReConFig 2011: 164-169
Coauthor Index
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