default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDVisvesh S. Sathe 0001
Visvesh Sathe 0001
Person information
- affiliation: University of Washington, Department of Electrical and Computer Engineering, Seattle, WA, USA
- affiliation (Ph.D.): University of Michigan, Ann Arbor, MI, USA
- affiliation (2007-2013): AMD, Santa Clara, CA, USA
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j20]Mike Shuo-Wei Chen
, Visvesh S. Sathe, Massimo Alioto, Jae-Sun Seo, Hidehiro Shiga:
Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 59(1): 4-7 (2024)- 2023
- [j19]Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe:
Regenerative Breaking: Optimal Energy Recycling for Energy Minimization in Duty-Cycled Domains. IEEE J. Solid State Circuits 58(1): 68-77 (2023) - 2022
- [j18]Chi-Hsiang Huang, Yidong Chen, Xun Sun, Arindam Mandal, Venkata Rajesh Pamula, Nasser A. Kurd, Visvesh S. Sathe:
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. IEEE J. Solid State Circuits 57(1): 90-102 (2022) - [c42]Deniz Dosluoglu, Kun-Da Chu, Diego Peña-Colaiocco, Ivan Zhao, Visvesh Sathe, Jacques C. Rudell:
A Reconfigurable Digital Beamforming V-Band Phased-Array Receiver. ESSCIRC 2022: 493-496 - [c41]Sumanth Gudaparthi, Sarabjeet Singh, Surya Narayanan, Rajeev Balasubramonian, Visvesh Sathe:
CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration. HPCA 2022: 876-891 - [c40]Diego Peña-Colaiocco, Chi-Hsiang Huang, Kun-Da Chu, Jacques Christophe Rudell, Visvesh S. Sathe:
An Optimal Digital Beamformer for mm-Wave Phased Arrays with 660MHz Instantaneous Bandwidth in 28nm CMOS. ISSCC 2022: 1-3 - [c39]Chi-Hsiang Huang, Arindam Mandal, Diego Peña-Colaiocco, Edevaldo Pereira Da Silva, Visvesh S. Sathe:
Energy Minimization of Duty-Cycled Systems Through Optimal Stored-Energy Recycling from Idle Domains. ISSCC 2022: 222-224 - [c38]James D. Rosenthal, Arindam Mandal, Visvesh Sathe, Matthew S. Reynolds:
An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS. RFID 2022: 109-113 - 2021
- [c37]Arindam Mandal, Diego Peña, Rajesh Pamula, Karam Khateeb, Logan Murphy, Azadeh Yazdan-Shahmorad, Steve I. Perlmutter, Forrest Pape, Jacques Christophe Rudell, Visvesh S. Sathe:
A 46-channel Vector Stimulator with 50mV Worst-Case Common-Mode Artifact for Low-Latency Adaptive Closed-Loop Neuromodulation. CICC 2021: 1-2 - [c36]Chi-Hsiang Huang, Xun Sun, Yidong Chen, Rajesh Pamula, Arindam Mandal, Visvesh Sathe:
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS. ISSCC 2021: 416-418 - 2020
- [j17]Fahim ur Rahman, Rajesh Pamula, Visvesh S. Sathe:
Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS. IEEE J. Solid State Circuits 55(2): 494-504 (2020) - [j16]Yi Shen, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Xin Xin, Shubin Liu, Zhangming Zhu, Visvesh Sathe, Nan Sun:
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. IEEE J. Solid State Circuits 55(3): 680-692 (2020) - [j15]John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Eric P. Pepin, Steve I. Perlmutter, Visvesh Sathe, Jacques Christophe Rudell:
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS. IEEE J. Solid State Circuits 55(7): 1749-1761 (2020) - [j14]John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Steve I. Perlmutter, Jacques Christophe Rudell, Visvesh S. Sathe:
A 0.0023 mm2/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression. IEEE Trans. Biomed. Circuits Syst. 14(2): 319-331 (2020) - [c35]Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe:
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS. VLSI Circuits 2020: 1-2 - [c34]Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe:
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j13]Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe:
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains. IEEE J. Solid State Circuits 54(4): 1173-1184 (2019) - [j12]Fahim ur Rahman, Greg Taylor, Visvesh Sathe:
A 1-2 GHz Computational-Locking ADPLL With Sub-20-Cycle Locktime Across PVT Variation. IEEE J. Solid State Circuits 54(9): 2487-2500 (2019) - [j11]Xun Sun, Fahim ur Rahman, Venkata Rajesh Pamula, Sung Kim, Xi Li, Naveen John, Visvesh S. Sathe:
An All-Digital Fused PLL-Buck Architecture for 82% Average Vdd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor. IEEE J. Solid State Circuits 54(11): 3215-3225 (2019) - [c33]Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun:
A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. CICC 2019: 1-4 - [c32]John P. Uehlin, William Anthony Smith, Venkata Rajesh Pamula, Steve I. Perlmutter, Visvesh Sathe, Jacques Christophe Rudell:
A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS. ESSCIRC 2019: 77-80 - [c31]Xun Sun, Akshat Boora, Wenbing Zhang, Venkata Rajesh Pamula, Visvesh Sathe:
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS. ISSCC 2019: 230-232 - [c30]Fahim ur Rahman, Rajesh Pamula, Akshat Boora, Xun Sun, Visvesh Sathe:
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS. ISSCC 2019: 312-314 - [i3]Sung Kim, Visvesh Sathe:
Bandwidth Extension on Raw Audio via Generative Adversarial Networks. CoRR abs/1903.09027 (2019) - 2018
- [j10]Fahim U. Rahman, Visvesh Sathe:
Quasi-Resonant Clocking: Continuous Voltage-Frequency Scalable Resonant Clocking System for Dynamic Voltage-Frequency Scaling Systems. IEEE J. Solid State Circuits 53(3): 924-935 (2018) - [j9]Vincent T. Lee, Armin Alaghi, Rajesh Pamula, Visvesh S. Sathe, Luis Ceze, Mark Oskin:
Architecture Considerations for Stochastic Computing Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2277-2289 (2018) - [j8]Sung Kim, Patrick Howe, Thierry Moreau, Armin Alaghi, Luis Ceze, Visvesh S. Sathe:
Energy-Efficient Neural Network Acceleration in the Presence of Bit-Level Memory Errors. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4285-4298 (2018) - [c29]Sung Kim, Patrick Howe, Thierry Moreau, Armin Alaghi, Luis Ceze, Visvesh Sathe:
MATIC: Learning around errors for efficient low-voltage neural network accelerators. DATE 2018: 1-6 - [c28]Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li, Naveen John, Visvesh S. Sathe:
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. ISSCC 2018: 302-304 - [c27]Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, Visvesh S. Sathe:
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. VLSI Circuits 2018: 1-2 - [c26]Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe:
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. VLSI Circuits 2018: 65-66 - 2017
- [c25]Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze:
Energy-efficient hybrid stochastic-binary neural networks for near-sensor computing. DATE 2017: 13-18 - [c24]Amrita Mazumdar, Thierry Moreau, Sung Kim, Meghan Cowan, Armin Alaghi, Luis Ceze, Mark Oskin, Visvesh Sathe:
Exploring computation-communication tradeoffs in camera systems. IISWC 2017: 177-186 - [i2]Vincent T. Lee, Armin Alaghi, John P. Hayes, Visvesh Sathe, Luis Ceze:
Energy-Efficient Hybrid Stochastic-Binary Neural Networks for Near-Sensor Computing. CoRR abs/1706.02344 (2017) - [i1]Amrita Mazumdar, Thierry Moreau, Sung Kim, Meghan Cowan, Armin Alaghi, Luis Ceze, Mark Oskin, Visvesh Sathe:
Exploring Computation-Communication Tradeoffs in Camera Systems. CoRR abs/1706.03864 (2017) - 2016
- [j7]Patrick Chiang, Visvesh S. Sathe:
Introduction to the Special Section on the 2015 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 51(8): 1733 (2016) - [j6]William Anthony Smith, Brian Mogen, Eberhard E. Fetz, Visvesh S. Sathe, Brian P. Otis:
Exploiting Electrocorticographic Spectral Characteristics for Optimized Signal Chain Design: A 1.08 Analog Front End With Reduced ADC Resolution Requirements. IEEE Trans. Biomed. Circuits Syst. 10(6): 1171-1180 (2016) - [c23]Ta-Tung Yen, Bin Yu, Visvesh S. Sathe:
All-digital hybrid-control buck converter for Integrated Voltage Regulator applications. DATE 2016: 567-570 - [c22]Samantak Gangopadhyay, Saad Bin Nasir, A. Subramanian, Visvesh Sathe, Arijit Raychowdhury:
UVFR: A Unified Voltage and Frequency Regulator with 500MHz/0.84V to 100KHz/0.27V operating range, 99.4% current efficiency and 27% supply guardband reduction. ESSCIRC 2016: 321-324 - [c21]Ali Najafi, Jacques Christophe Rudell, Visvesh Sathe:
Regenerative Breaking: Recovering Stored Energy from Inactive Voltage Domains for Energy-efficient Systems-on-Chip. ISLPED 2016: 94-99 - [c20]Fahim U. Rahman, Visvesh S. Sathe:
19.6 voltage-scalable frequency-independent quasi-resonant clocking implementation of a 0.7-to-1.2V DVFS System. ISSCC 2016: 334-335 - [c19]Visvesh Sathe, Andrew Marshall:
Tutorial 4A: Supply voltage noise and mitigation for real world SoCs. SoCC 2016: 1-3 - 2015
- [c18]Xiaoyang Mi, Debashis Mandal, Visvesh S. Sathe, Bertan Bakkaloglu, Jae-sun Seo:
Fully-integrated switched-capacitor voltage regulator with on-chip current-sensing and workload optimization in 32nm SOI CMOS. ISLPED 2015: 140-145 - [c17]Visvesh S. Sathe, Jae-sun Seo:
Analysis and optimization of CMOS switched-capacitor converters. ISLPED 2015: 327-334 - 2014
- [c16]Visvesh S. Sathe:
Quasi-resonant clocking: a run-time control approach for true voltage-frequency-scalability. ISLPED 2014: 87-92 - [c15]Kannan A. Sankaragomathi, William Anthony Smith, Brian P. Otis, Visvesh S. Sathe:
A deterministic-dither-based, all-digital system for on-chippower supply noise measurement. ISLPED 2014: 283-286 - 2013
- [j5]Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger:
Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. IEEE J. Solid State Circuits 48(1): 140-149 (2013) - [c14]Visvesh S. Sathe, Arif Rahman:
Energy efficient SoC design. CICC 2013: 1 - 2012
- [j4]Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou:
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 977-988 (2012) - [c13]Steven J. E. Wilton, Visvesh S. Sathe:
Advances in 3D design and optimization. CICC 2012: 1 - [c12]Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger:
Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC 2012: 68-70 - 2010
- [j3]Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou:
187 MHz Subthreshold-Supply Charge-Recovery FIR. IEEE J. Solid State Circuits 45(4): 793-803 (2010) - [c11]Hanh-Phuc Le, Michael D. Seeman, Seth Sanders, Visvesh S. Sathe, Samuel Naffziger, Elad Alon:
A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency. ISSCC 2010: 210-211
2000 – 2009
- 2009
- [c10]Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou:
A charge-recovery 600MHz FIR filter with 1.5-cycle latency overhead. ESSCIRC 2009: 160-163 - [c9]Alexander T. Ishii, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou:
A resonant-clock 200MHz ARM926EJ-STM microcontroller. ESSCIRC 2009: 356-359 - 2008
- [j2]Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou:
Resonant-Clock Latch-Based Design. IEEE J. Solid State Circuits 43(4): 864-873 (2008) - 2007
- [j1]Visvesh S. Sathe, Juang-Ying Chueh, Marios C. Papaefthymiou:
Energy-Efficient GHz-Class Charge-Recovery Logic. IEEE J. Solid State Circuits 42(1): 38-47 (2007) - [c8]Visvesh S. Sathe, Jerry C. Kao, Marios C. Papaefthymiou:
A 0.8-1.2GHz Single-Phase Resonant-Clocked FIR Filter with Level-Sensitive Latches. CICC 2007: 583-586 - 2006
- [c7]Juang-Ying Chueh, Visvesh S. Sathe, Marios C. Papaefthymiou:
900MHz to 1.2GHz Two-Phase Resonant Clock Network with Programmable Driver and Loading. CICC 2006: 777-780 - [c6]Visvesh S. Sathe, Juang-Ying Chueh, Marios Papaefthymio:
A 1.1ghz charge-recovery logic. ISSCC 2006: 1540-1549 - 2005
- [c5]Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou:
Fast, efficient, recovering, and irreversible. Conf. Computing Frontiers 2005: 407-413 - [c4]Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler:
A GHz-class charge recovery logic. ISLPED 2005: 91-94 - [c3]Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler:
Boost Logic: A High Speed Energy Recovery Circuit Family. ISVLSI 2005: 22-27 - 2004
- [c2]Visvesh S. Sathe, Conrad H. Ziesler, Marios C. Papaefthymiou, Suhwan Kim, Stephen V. Kosonocky:
A synchronous interface for SoCs with multiple clock domains. SoCC 2004: 173-174 - 2003
- [c1]Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou:
A 225 MHz resonant clocked ASIC chip. ISLPED 2003: 48-53
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 21:25 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
