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ORCIDParitosh K. Pandya
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- affiliation: Tata Institute of Fundamental Research, Mumbai, India
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2020 – today
- 2024
[i18]Shankara Narayanan Krishna, Khushraj Madnani, Agnipratim Nag, Paritosh K. Pandya:
Openness And Partial Adjacency In One Variable TPTL. CoRR abs/2411.00117 (2024)- 2023
- [b1]Gopinath Karmakar, Amol Wakankar, Ashutosh Kabra, Paritosh K. Pandya:
Development of Safety-Critical Systems - Architecture and Software. Springer 2023, ISBN 978-3-031-27900-3, pp. 1-326 - [j10]Shankara Narayanan Krishna
, Khushraj Madnani, Manuel Mazo Jr., Paritosh K. Pandya:
From Non-punctuality to Non-adjacency: A Quest for Decidability of Timed Temporal Logics with Quantifiers. Formal Aspects Comput. 35(2): 9:1-9:50 (2023) - [c50]Shankara Narayanan Krishna, Khushraj Nanik Madnani, Rupak Majumdar, Paritosh K. Pandya:
Satisfiability Checking of Multi-Variable TPTL with Unilateral Intervals Is PSPACE-Complete. CONCUR 2023: 23:1-23:18 - [i17]Shankara Narayanan Krishna, Khushraj Nanik Madnani, Rupak Majumdar, Paritosh K. Pandya:
Satisfiability Checking of Multi-Variable TPTL with Unilateral Intervals Is PSPACE-Complete. CoRR abs/2309.00386 (2023) - 2022
- [j9]Paritosh K. Pandya, Amol Wakankar:
Specification and optimal reactive synthesis of run-time enforcement shields. Inf. Comput. 285(Part): 104865 (2022) - 2021
- [c49]Shankara Narayanan Krishna, Khushraj Madnani, Manuel Mazo Jr., Paritosh K. Pandya:
Generalizing Non-punctuality for Timed Temporal Logic with Freeze Quantifiers. FM 2021: 182-199 - [i16]Shankara Narayanan Krishna, Khushraj Madnani, Manuel Mazo Jr., Paritosh K. Pandya:
Generalizing Non-Punctuality for Timed Temporal Logic with Freeze Quantifiers. CoRR abs/2105.09534 (2021) - [i15]Shankara Narayanan Krishna, Khushraj Nanik Madnani, Manuel Mazo Jr., Paritosh K. Pandya:
Logics Meet 2-Way 1-Clock Alternating Timed Automata. CoRR abs/2107.12986 (2021) - 2020
- [j8]Andreas Krebs, Kamal Lodaya, Paritosh K. Pandya, Howard Straubing:
Two-variable logics with some betweenness relations: Expressiveness, satisfiability and membership. Log. Methods Comput. Sci. 16(3) (2020)
2010 – 2019
- 2019
- [c48]Paritosh K. Pandya, Amol Wakankar:
Logical specification and uniform synthesis of robust controllers. MEMOCODE 2019: 15:1-15:11 - [c47]Amol Wakankar, Paritosh K. Pandya, Raj Mohan Matteplackel:
DCSynth: Guided Reactive Synthesis with Soft Requirements. VSTTE 2019: 124-142 - [c46]Paritosh K. Pandya, Amol Wakankar:
Specification and Optimal Reactive Synthesis of Run-time Enforcement Shields. GandALF 2019: 91-106 - [i14]Andreas Krebs, Kamal Lodaya, Paritosh K. Pandya, Howard Straubing:
Two-variable logics with some betweenness relations: Expressiveness, satisfiability and membership. CoRR abs/1902.05905 (2019) - [i13]Amol Wakankar, Paritosh K. Pandya, Raj Mohan Matteplackel:
DCSYNTH: A Tool for Guided Reactive Synthesis with Soft Requirements. CoRR abs/1903.03991 (2019) - [i12]Paritosh K. Pandya, Amol Wakankar:
Specification and Reactive Synthesis of Robust Controllers. CoRR abs/1905.11157 (2019) - 2018
- [c45]Shankara Narayanan Krishna, Khushraj Madnani, Paritosh K. Pandya:
Logics Meet 1-Clock Alternating Timed Automata. CONCUR 2018: 39:1-39:17 - [c44]Andreas Krebs, Kamal Lodaya, Paritosh K. Pandya, Howard Straubing:
An Algebraic Decision Procedure for Two-Variable Logic with a Between Relation. CSL 2018: 28:1-28:17 - [e2]Sumit Ganguly, Paritosh K. Pandya:
38th IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science, FSTTCS 2018, December 11-13, 2018, Ahmedabad, India. LIPIcs 122, Schloss Dagstuhl - Leibniz-Zentrum für Informatik 2018, ISBN 978-3-95977-093-4 [contents] - [i11]Shankara Narayanan Krishna, Khushraj Madnani, Paritosh K. Pandya:
Büchi-Kamp Theorems for 1-clock ATA. CoRR abs/1802.02514 (2018) - 2017
- [c43]Shankara Narayanan Krishna, Khushraj Madnani, Paritosh K. Pandya:
Making Metric Temporal Logic Rational. MFCS 2017: 77:1-77:14 - [c42]Raj Mohan Matteplackel, Paritosh K. Pandya, Amol Wakankar:
Formalizing Timing Diagram Requirements in Discrete Duration Calculus. SEFM 2017: 253-268 - [c41]Kamal Lodaya, Paritosh K. Pandya:
Deterministic Temporal Logics and Interval Constraints. M4M@ICLA 2017: 23-40 - [i10]Shankara Narayanan Krishna, Khushraj Madnani, Paritosh K. Pandya:
Making Metric Temporal Logic Rational. CoRR abs/1705.01501 (2017) - [i9]Raj Mohan Matteplackel, Paritosh K. Pandya, Amol Wakankar:
Formalizing Timing Diagram Requirements in Discrete Duration Calulus. CoRR abs/1705.04510 (2017) - [i8]Amol Wakankar, Paritosh K. Pandya, Raj Mohan Matteplackel:
DCSYNTH: Guided Reactive Synthesis with Soft Requirements for Robust Controller and Shield Synthesis. CoRR abs/1711.01823 (2017) - 2016
- [c40]Shankara Narayanan Krishna, Khushraj Madnani, Paritosh K. Pandya:
Metric Temporal Logic with Counting. FoSSaCS 2016: 335-352 - [c39]Andreas Krebs, Kamal Lodaya, Paritosh K. Pandya, Howard Straubing:
Two-variable Logic with a Between Relation. LICS 2016: 106-115 - [i7]Andreas Krebs, Kamal Lodaya, Paritosh K. Pandya, Howard Straubing:
Two-variable Logic with a Between Predicate. CoRR abs/1603.05625 (2016) - 2015
- [i6]Khushraj Madnani, Shankara Narayanan Krishna, Paritosh K. Pandya:
Metric Temporal Logic with Counting. CoRR abs/1512.09032 (2015) - 2014
- [c38]Khushraj Madnani, Shankara Narayanan Krishna, Paritosh K. Pandya:
On Unary Fragments of MTL and TPTL over Timed Words. ICTAC 2014: 333-350 - [c37]Khushraj Madnani, Shankara Narayanan Krishna, Paritosh K. Pandya:
Partially Punctual Metric Temporal Logic is Decidable. TIME 2014: 174-183 - [i5]Paritosh K. Pandya, Simoni S. Shah:
Deterministic Logics for UL. CoRR abs/1401.2714 (2014) - [i4]Khushraj Madnani, Shankara Narayanan Krishna, Paritosh K. Pandya:
Partially Punctual Metric Temporal Logic is Decidable. CoRR abs/1404.6965 (2014) - 2013
- [c36]Paritosh K. Pandya, Simoni S. Shah:
Deterministic Logics for UL. ICTAC 2013: 301-318 - [i3]Paritosh K. Pandya, Simoni S. Shah:
The Unary Fragments of Metric Interval Temporal Logic: Bounded versus Lower bound Constraints (Full Version). CoRR abs/1305.3204 (2013) - [i2]Khushraj Madnani, Shankara Narayanan Krishna, Paritosh K. Pandya:
On the Decidability and Complexity of Some Fragments of Metric Temporal Logic. CoRR abs/1305.6137 (2013) - 2012
- [c35]Paritosh K. Pandya, Simoni S. Shah:
The Unary Fragments of Metric Interval Temporal Logic: Bounded versus Lower Bound Constraints. ATVA 2012: 77-91 - [p2]Paritosh K. Pandya, P. Vijay Suman:
An Introduction to Timed Automata. Modern Applications of Automata Theory 2012: 111-148 - [p1]Ajesh Babu, Paritosh K. Pandya:
Chop Expressions and Discrete Duration Calculus. Modern Applications of Automata Theory 2012: 229-256 - 2011
- [c34]Paritosh K. Pandya, Simoni S. Shah:
On Expressive Powers of Timed Logics: Comparing Boundedness, Non-punctuality, and Deterministic Freezing. CONCUR 2011: 60-75 - [c33]Dileep Raghunath Kini, Shankara Narayanan Krishna, Paritosh K. Pandya:
On Construction of Safety Signal Automata for $MITL[\: \mathcal{U}, \: \mathcal{S}]$ Using Temporal Projections. FORMATS 2011: 225-239 - [i1]Paritosh K. Pandya, Simoni S. Shah:
On Expressive Powers of Timed Logics: Comparing Boundedness, Non-punctuality and Deterministic Freezing. CoRR abs/1102.5638 (2011) - 2010
- [c32]Kamal Lodaya, Paritosh K. Pandya, Simoni S. Shah:
Around Dot Depth Two. Developments in Language Theory 2010: 303-315 - [c31]Paritosh K. Pandya, Simoni S. Shah:
Unambiguity in Timed Regular Languages: Automata and Logics. FORMATS 2010: 168-182
2000 – 2009
- 2009
- [c30]P. Vijay Suman, Paritosh K. Pandya:
Determinization and Expressiveness of Integer Reset Timed Automata with Silent Transitions. LATA 2009: 728-739 - 2008
- [j7]Dina Thomas, Supratik Chakraborty, Paritosh K. Pandya:
Efficient guided symbolic reachability using reachability expressions. Int. J. Softw. Tools Technol. Transf. 10(2): 113-129 (2008) - [c29]Swarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. Ramesh, P. Vijay Suman, Paritosh K. Pandya, Shengbing Jiang:
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts. DAC 2008: 296-299 - [c28]P. Vijay Suman, Paritosh K. Pandya, Shankara Narayanan Krishna, Lakshmi Manasa:
Timed Automata with Integer Resets: Language Inclusion and Expressiveness. FORMATS 2008: 78-92 - [c27]Kamal Lodaya, Paritosh K. Pandya, Simoni S. Shah:
Marking the chops: an unambiguous temporal logic. IFIP TCS 2008: 461-476 - [c26]P. Vijay Suman, Paritosh K. Pandya:
Timed and Hybrid Automata in SAL. SYNASC 2008: 480-486 - 2007
- [c25]Paritosh K. Pandya, Shankara Narayanan Krishna, Kuntal Loya:
On Sampling Abstraction of Continuous Time Logic with Durations. TACAS 2007: 246-260 - 2006
- [c24]Raman Kazhamiakin, Paritosh K. Pandya, Marco Pistore:
Timed Modelling and Analysis in Web Service Compositions. ARES 2006: 840-846 - [c23]Kamal Lodaya, Paritosh K. Pandya:
A Dose of Timed Logic, in Guarded Measure. FORMATS 2006: 260-273 - [c22]Raman Kazhamiakin, Paritosh K. Pandya, Marco Pistore:
Representation, Verification, and Computation of Timed Properties in Web. ICWS 2006: 497-504 - [c21]Dina Thomas, Supratik Chakraborty, Paritosh K. Pandya:
Efficient Guided Symbolic Reachability Using Reachability Expressions. TACAS 2006: 120-134 - 2005
- [c20]Shankara Narayanan Krishna, Paritosh K. Pandya:
Modal Strength Reduction in Quantified Discrete Duration Calculus. FSTTCS 2005: 444-456 - [c19]Babita Sharma, Paritosh K. Pandya, Supratik Chakraborty:
Bounded Validity Checking of Interval Duration Logic. TACAS 2005: 301-316 - 2004
- [c18]Paritosh K. Pandya:
Finding Extremal Models of Discrete Duration Calculus formulae using Symbolic Search. AVoCS 2004: 247-262 - 2003
- [c17]Gaurav Chakravorty, Paritosh K. Pandya:
Digitizing Interval Duration Logic. CAV 2003: 167-179 - [e1]Paritosh K. Pandya, Jaikumar Radhakrishnan:
FST TCS 2003: Foundations of Software Technology and Theoretical Computer Science, 23rd Conference, Mumbai, India, December 15-17, 2003, Proceedings. Lecture Notes in Computer Science 2914, Springer 2003, ISBN 3-540-20680-9 [contents] - 2002
- [c16]Paritosh K. Pandya:
The Saga of Synchronous Bus Arbiter: On Model Checking Quantitative Timing Properties of Synchronous Programs. SLAP@ETAPS 2002: 110-124 - [c15]Paritosh K. Pandya:
Interval Duration Logic: Expressiveness and Decidability. Theory and Practice of Timed Systems @ ETAPS 2002: 254-272 - 2001
- [c14]Paritosh K. Pandya:
Model Checking CTL*[DC]. TACAS 2001: 559-573
1990 – 1999
- 1998
- [c13]Paritosh K. Pandya, Y. S. Ramakrishna:
Recursive Mean-Value Calculus. FSTTCS 1998: 257-268 - [c12]Paritosh K. Pandya, Dang Van Hung:
Duration Calculus of Weakly Monotonic Time. FTRTFT 1998: 55-64 - [c11]Manoranjan Satpathy, Dang Van Hung, Paritosh K. Pandya:
Some Decidability Results for Duration Calculus under Synchronous Interpretation. FTRTFT 1998: 186-197 - [c10]Paritosh K. Pandya, H.-P. Wang, Qiwen Xu:
Toward a theory of sequential hybrid programs. PROCOMET 1998: 366-384 - 1996
- [c9]Paritosh K. Pandya:
Weak Chop Inverses and Liveness in Mean-Value Calculus. FTRTFT 1996: 148-167 - 1995
- [j6]Michael R. Hansen, Paritosh K. Pandya, Zhou Chaochen:
Finite Divergence. Theor. Comput. Sci. 138(1): 113-139 (1995) - [c8]Paritosh K. Pandya:
Some Extensions to Propositional Mean-Value Caculus: Expressiveness and Decidability. CSL 1995: 434-451 - 1994
- [c7]K. Narayan Kumar, Paritosh K. Pandya:
On the Computational Power of Operators in ICSP with Fairness. FSTTCS 1994: 231-242 - [c6]Huiqun Yu, Paritosh K. Pandya, Yongqiang Sun:
A Calculus for Hybrid Sampled Data Systems. FTRTFT 1994: 716-737 - [c5]Xinyao Yu, Ji Wang, Chaochen Zhou, Paritosh K. Pandya:
Formal Design of Hybrid Systems. FTRTFT 1994: 738-755 - 1993
- [j5]K. Narayan Kumar, Paritosh K. Pandya:
Infinitary Parallelism without Unbounded Nondeterminism in CSP. Acta Informatica 30(5): 467-487 (1993) - [c4]M. R. K. Krishna Rao, Paritosh K. Pandya, R. K. Shyamasundar:
Verification Tools in the Development of Provably Correct Compilers. FME 1993: 442-461 - [c3]K. Narayan Kumar, Paritosh K. Pandya:
ICSP and Its Relationship with ACSP and CSP. FSTTCS 1993: 358-372 - 1992
- [j4]Paul H. B. Gardiner, Paritosh K. Pandya:
Reasoning Algebraically about Recursion. Sci. Comput. Program. 18(3): 271-280 (1992) - 1991
- [j3]Paritosh K. Pandya, Mathai Joseph:
P - A Logic - A Compositional Proof System for Distributed Programs. Distributed Comput. 5: 37-54 (1991) - 1990
- [c2]Jonathan P. Bowen, Jifeng He, Paritosh K. Pandya:
An Approach to Verifiable Compiling Specification and Prototyping. PLILP 1990: 45-59
1980 – 1989
- 1989
- [c1]Paritosh K. Pandya:
Some Comments on the Assumption-Commitment Framework for Compositional Verification of Distributed Programs. REX Workshop 1989: 622-640 - 1986
- [j2]Mathai Joseph, Paritosh K. Pandya:
Finding Response Times in a Real-Time System. Comput. J. 29(5): 390-395 (1986) - [j1]Paritosh K. Pandya, Mathai Joseph:
A Structure-Directed Total Correctness Proof Rule for Recursive Procedure Calls. Comput. J. 29(6): 531-537 (1986)
Coauthor Index
aka: Shankara Narayanan Krishna
aka: Khushraj Nanik Madnani
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